Atomistic Insights on the Full Operation Cycle of a HfO2-Based Resistive Random Access Memory Cell from Molecular Dynamics

Abstract3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems.

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Temperature effects on an HfO2-TiO2-HfO2 stack layer resistive random access memory cell for low power applications

2020 5th International Conference on Devices, Circuits and Systems (ICDCS) ◽

10.1109/icdcs48716.2020.243597 ◽

2020 ◽

Author(s):

A. Napolean ◽

N.M. Sivamangai ◽

R. NaveenKumar

Keyword(s):

Low Power ◽

Temperature Effects ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Access Memory

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Analysis of Leakage Current of HfO2/TaOx-Based 3-D Vertical Resistive Random Access Memory Array

Micromachines ◽

10.3390/mi12060614 ◽

2021 ◽

Vol 12 (6) ◽

pp. 614

Author(s):

Zhisheng Chen ◽

Renjun Song ◽

Qiang Huo ◽

Qirui Ren ◽

Chenrui Zhang ◽

...

Keyword(s):

Leakage Current ◽

Current Model ◽

Random Access ◽

Memory Cell ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Memory Storage ◽

Access Memory ◽

Leakage Currents ◽

The Impact

Three-dimensional vertical resistive random access memory (VRRAM) is proposed as a promising candidate for increasing resistive memory storage density, but the performance evaluation mechanism of 3-D VRRAM arrays is still not mature enough. The previous approach to evaluating the performance of 3-D VRRAM was based on the write and read margin. However, the leakage current (LC) of the 3-D VRRAM array is a concern as well. Excess leakage currents not only reduce the read/write tolerance and liability of the memory cell but also increase the power consumption of the entire array. In this article, a 3-D circuit HSPICE simulation is used to analyze the impact of the array size and operation voltage on the leakage current in the 3-D VRRAM architecture. The simulation results show that rapidly increasing leakage currents significantly affect the size of 3-D layers. A high read voltage is profitable for enhancing the read margin. However, the leakage current also increases. Alleviating this conflict requires a trade-off when setting the input voltage. A method to improve the array read/write efficiency is proposed by analyzing the influence of the multi-bit operations on the overall leakage current. Finally, this paper explores different methods to reduce the leakage current in the 3-D VRRAM array. The leakage current model proposed in this paper provides an efficient performance prediction solution for the initial design of 3-D VRRAM arrays.

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Models Comparison And Validation With the Experimental Nano- Scale Silicon Substrate Based Annealed Pt/HfO2/Pt Resistive Random Access Memory Cell

10.21203/rs.3.rs-704249/v1 ◽

2021 ◽

Author(s):

Napolean A ◽

Sivamangai NM ◽

Nithya N ◽

Naveenkumar R

Keyword(s):

Silicon Substrate ◽

Random Access ◽

Single Layer ◽

Memory Cell ◽

Random Access Memory ◽

Resistive Random Access Memory ◽

Experimental Result ◽

Access Memory ◽

Novel Device ◽

Models Comparison

Abstract Metal oxide resistive random access memory (RRAM) is a novel device that provides an alternate solution for existing CMOS memory devices. In RRAM, correlate the experimental result with a simulated result by a unique model is a critical task. This work focused on the validation of silicon substrate-based fabricated single layer annealed and electroformed at 80oC ambient temperature (A-80) RRAM cell. The experimental result concludes that the proposed Pt/HfO2/Pt device provides the forming voltage of 3.8 V, Vset = 1.7 V, and Vreset=-0.8 V. Switching results are compared with the simulated result which is working based on non-linear ion drift, Yakopcic and voltage threshold adaptive memristor (VTEAM) models. VTEAM model gives a closure relationship with experimental data and well suited for our fabricated device. Further, the VTEAM model is modified to contribute accurate results and one of the standard model metrics, accuracy is analysed for a modified VTEAM model. Statistical analysis proves that, the mean error percentage of modified VTEAM and VTEAM models against experimental outcomes are 21.4% and 25.3 % respectively

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