scholarly journals Quantum random number generator using a cloud superconducting quantum computer based on source-independent protocol

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Yuanhao Li ◽  
Yangyang Fei ◽  
Weilong Wang ◽  
Xiangdong Meng ◽  
Hong Wang ◽  
...  

AbstractQuantum random number generator (QRNG) relies on the intrinsic randomness of quantum mechanics to produce true random numbers which are important in information processing tasks. Due to the presence of the superposition state, a quantum computer can be used as a true random number generator. However, in practice, the implementation of the quantum computer is subject to various noise sources, which affects the randomness of the generated random numbers. To solve this problem, we propose a scheme based on the quantum computer which is motivated by the source-independent QRNG scheme in optics. By using a method to estimate the upper bound of the superposition state preparation error, the scheme can provide certified randomness in the presence of readout errors. To increase the generation rate of random bits, we also provide a parameter optimization method with a finite data size. In addition, we experimentally demonstrate our scheme on the cloud superconducting quantum computers of IBM.

2021 ◽  
Author(s):  
Yuanhao Li ◽  
Weilong Wang ◽  
Yangyang Fei ◽  
Xiangdong Meng ◽  
Hong Wang ◽  
...  

Abstract Quantum random number generator (QRNG) relies on the intrinsic randomness of quantum mechanics to produce true random numbers which are important in information processing tasks. Due to the presence of the superposition state, quantum computer can be used as a true random number generator. However, in practice, the implementation of quantum computer is subject to various noise sources which affect the randomness of the generated random numbers. To solve this problem, we propose a source-independent QRNG (SI-QRNG) scheme based on quantum computer which is motivated by the SI-QRNG scheme in quantum optics. The scheme can provide certified randomness by estimating the preparation error of superposition states in real time even when the source is untrusted, under the assumption that the measurement operation is trusted. Our analysis takes into account the readout error of quantum state and further gives the final extracted number of random bits. And the estimation method of preparation error of superposition state in randomness source. We also provide a parameter optimization method to increase the generation rate of random bits. In addition, by utilizing the cloud superconducting quantum computer of IBM, we experimentally demonstrate the practicality of our SI-QRNG scheme and achieve the generation of true random numbers.


Author(s):  
Kentaro Tamura ◽  
Yutaka Shikano

Abstract A cloud quantum computer is similar to a random number generator in that its physical mechanism is inaccessible to its users. In this respect, a cloud quantum computer is a black box. In both devices, its users decide the device condition from the output. A framework to achieve this exists in the field of random number generation in the form of statistical tests for random number generators. In the present study, we generated random numbers on a 20-qubit cloud quantum computer and evaluated the condition and stability of its qubits using statistical tests for random number generators. As a result, we observed that some qubits were more biased than others. Statistical tests for random number generators may provide a simple indicator of qubit condition and stability, enabling users to decide for themselves which qubits inside a cloud quantum computer to use.


Micromachines ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 31
Author(s):  
Junxiu Liu ◽  
Zhewei Liang ◽  
Yuling Luo ◽  
Lvchen Cao ◽  
Shunsheng Zhang ◽  
...  

Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic map is optimised by using the perturbation operation which effectively reduces the degradation of digital chaos. By employing stochastic computing, a hardware PRNG is designed with relatively low hardware utilisation. The proposed hardware PRNG is implemented by using a Field Programmable Gate Array device. Results show that the chaotic map achieves good security performance by using the perturbation operations and the generated pseudo-random numbers pass the TestU01 test and the NIST SP 800-22 test. Most importantly, it also saves 89% of hardware resources compared to conventional approaches.


Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1831
Author(s):  
Binbin Yang ◽  
Daniel Arumí ◽  
Salvador Manich ◽  
Álvaro Gómez-Pau ◽  
Rosa Rodríguez-Montañés ◽  
...  

In this paper, the modulation of the conductance levels of resistive random access memory (RRAM) devices is used for the generation of random numbers by applying a train of RESET pulses. The influence of the pulse amplitude and width on the device resistance is also analyzed. For each pulse characteristic, the number of pulses required to drive the device to a particular resistance threshold is variable, and it is exploited to extract random numbers. Based on this behavior, a random number generator (RNG) circuit is proposed. To assess the performance of the circuit, the National Institute of Standards and Technology (NIST) randomness tests are applied to evaluate the randomness of the bitstreams obtained. The experimental results show that four random bits are simultaneously obtained, passing all the applied tests without the need for post-processing. The presented method provides a new strategy to generate random numbers based on RRAMs for hardware security applications.


2020 ◽  
Author(s):  
Gwangmin Kim ◽  
Jae Hyun In ◽  
Hakseung Rhee ◽  
Woojoon Park ◽  
Hanchan Song ◽  
...  

Abstract The intrinsic stochasticity of the memristor can be used to generate true random numbers, essential for non-decryptable hardware-based security devices. Here we propose a novel and advanced method to generate true random numbers utilizing the stochastic oscillation behavior of a NbOx mott memristor, exhibiting self-clocking, fast and variation tolerant characteristics. The random number generation rate of the device can be at least 40 kbs-1, which is the fastest record compared with previous volatile memristor-based TRNG devices. Also, its dimensionless operating principle provides high tolerance against both ambient temperature variation and device-to-device variation, enabling robust security hardware applicable in harsh environments.


Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 1869 ◽  
Author(s):  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Francesco Falaschi ◽  
Matteo Bertolucci ◽  
Jacopo Belli ◽  
...  

In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.


2012 ◽  
Vol 2012 ◽  
pp. 1-9 ◽  
Author(s):  
Wang Xingyuan ◽  
Qin Xue ◽  
Teng Lin

We propose a novel true random number generator using mouse movement and a one-dimensional chaotic map. We utilize thex-coordinate of the mouse movement to be the length of an iteration segment of our TRNs and they-coordinate to be the initial value of this iteration segment. And, when it iterates, we perturb the parameter with the real value produced by the TRNG itself. And we find that the TRNG we proposed conquers several flaws of some former mouse-based TRNGs. At last we take experiments and test the randomness of our algorithm with the NIST statistical test suite; results illustrate that our TRNG is suitable to produce true random numbers (TRNs) on universal personal computers (PCs).


2003 ◽  
Vol 13 (1) ◽  
pp. 235-240
Author(s):  
SIMON PEYTON JONES

27.1 The RandomGen class, and the StdGen generator  23627.2 The Random class  23927.3 The global random number generator  240


2015 ◽  
Vol 61 (2) ◽  
pp. 199-204 ◽  
Author(s):  
Szymon Łoza ◽  
Łukasz Matuszewski ◽  
Mieczysław Jessa

Abstract Today, cryptographic security depends primarily on having strong keys and keeping them secret. The keys should be produced by a reliable and robust to external manipulations generators of random numbers. To hamper different attacks, the generators should be implemented in the same chip as a cryptographic system using random numbers. It forces a designer to create a random number generator purely digitally. Unfortunately, the obtained sequences are biased and do not pass many statistical tests. Therefore an output of the random number generator has to be subjected to a transformation called post-processing. In this paper the hash function SHA-256 as post-processing of bits produced by a combined random bit generator using jitter observed in ring oscillators (ROs) is proposed. All components – the random number generator and the SHA-256, are implemented in a single Field Programmable Gate Array (FPGA). We expect that the proposed solution, implemented in the same FPGA together with a cryptographic system, is more attack-resistant owing to many sources of randomness with significantly different nominal frequencies.


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