Glass Grinding and Polishing

The paintings by the great Hungarian master Mihaly Munkacsy (1844-1900) made in an 8-9 years period of his activity are deteriorating. The most conspicuous sign of the deterioration is an intensive darkening. We have made an attempt by electron beam microanalysis to clarify the causes of the darkening. The importance of a study like this is increased by the fact that a similar darkening can be observed on the paintings by Munkacsy’s contemporaries e.g Courbet and Makart. A thick brown mass the so called bitumen used by Munkacsy for grounding and also as a paint is believed by the art historians to cause the darkening.For this study, paint specimens were taken from the following paintings: “Studio”, “Farewell” and the “Portrait of the Master’s Wife”, all of them are the property of the Hungarian National Gallery. The paint samples were embedded in a polyester resin “Poly-Pol PS-230” and after grinding and polishing their cross section was used for x-ray mapping.

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Electrical Invasiveness of Grinding and Polishing Silicon Integrated Circuits Down to 1 μm Remaining Silicon Thickness

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0166 ◽

2016 ◽

Author(s):

Robert Chivas ◽

Scott Silverman ◽

Michael DiBattista ◽

Ulrike Kindereit

Keyword(s):

Integrated Circuits ◽

Failure Analysis ◽

Electron Hole ◽

Analysis Techniques ◽

Silicon Integrated Circuits ◽

Electron Hole Pair ◽

Pair Generation ◽

Silicon Thickness ◽

Performance Timing ◽

Grinding And Polishing

Abstract Anticipating the end of life for IR-based failure analysis techniques, a method of global backside preparation to ultra-thin remaining silicon thickness (RST) has been developed. When the remaining silicon is reduced, some redistribution of stress is expected, possibly altering the performance (timing) of integrated circuits in addition to electron-hole pair generation. In this work, a study of the electrical invasiveness due to grinding and polishing silicon integrated circuits to ultra-thin (< 5 um global, ~ 1 um local) remaining thickness is presented.

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Research on the Key Technology Application of Industrial Robot in Grinding and Polishing of Pen and Electronic Industry

Journal of Physics Conference Series ◽

10.1088/1742-6596/1699/1/012012 ◽

2020 ◽

Vol 1699 ◽

pp. 012012

Author(s):

Yunxia Qi

Keyword(s):

Industrial Robot ◽

Electronic Industry ◽

Technology Application ◽

Key Technology ◽

Grinding And Polishing

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Preparation of Large Area Cross-Sectional Tem Specimen of Semiconducting Heteroepitaxial Materials

MRS Proceedings ◽

10.1557/proc-254-201 ◽

1991 ◽

Vol 254 ◽

Cited By ~ 3

Author(s):

M. Tamura ◽

S. Aoki

Keyword(s):

Sample Preparation ◽

Film Growth ◽

General Information ◽

One Dimension ◽

Main Principle ◽

Large Area ◽

Cross Sectional ◽

Growth Modes ◽

Present Technique ◽

Grinding And Polishing

AbstractThe sample preparation procedures which enable us to observe large areas over a few tens of microns in one-dimension of semiconducting heteroepitaxial materials are described. The main principle involves the careful grinding and polishing of samples. In these procedures, another side thinning of the specimen after finishing initial side polishing is carried out using a sample platform by hand throughout all of the following steps. It is shown that for some typical examples of heteroepitaxial films general information concerning the film growth modes and structures, as well as the defect morphologies and natures introduced during growth can be effectively obtained by using the present technique.

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