Negative bias temperature stress and annealing effects in p-channel power VDMOSFETs

2008 ◽  
Author(s):  
D. Dankovic ◽  
I. Manic ◽  
V. Davidovic ◽  
S. Djoric-Veljkovic ◽  
S. Golubovic ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Negative Bias ◽  
Channel Power ◽  
Annealing Effects ◽  
Bias Temperature Stress

Characteristics of Traps Induced by Hot Holes Under Negative-Bias Temperature Stress in a pMOSFET

2009 ◽  
Vol 30 (11) ◽  
pp. 1194-1196 ◽  
Author(s):  
Minseok Jo ◽  
Man Chang ◽  
Seonghyun Kim ◽  
Seungjae Jung ◽  
Ju-Bong Park ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Negative Bias ◽  
Bias Temperature Stress

Drain Bias Effect on the Interface Traps of pMOSFETs under Negative Bias Temperature Stress

2019 ◽  
Vol 18 (1) ◽  
pp. 219-223
Author(s):  
Junyan Pan ◽  
Jiaqi Yang ◽  
Ying Qiao ◽  
X.Y. Liu ◽  
Ruqi Han ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Negative Bias ◽  
Interface Traps ◽  
Bias Effect ◽  
Drain Bias ◽  
Bias Temperature Stress

Investigation of the instability of low-temperature poly-silicon thin film transistors under a negative bias temperature stress

2013 ◽  
Vol 9 (S1) ◽  
pp. 13-16 ◽  
Author(s):  
Yu-Mi Kim ◽  
Kwang-Seok Jeong ◽  
Ho-Jin Yun ◽  
Seung-Dong Yang ◽  
Sang-Youl Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Low Temperature ◽  
Temperature Stress ◽  
Thin Film Transistors ◽  
Negative Bias ◽  
Silicon Thin Film ◽  
Poly Silicon ◽  
Bias Temperature Stress
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