Direct conversion RF front-end with a low-power consumption technique for 2.4 GHz ISM band

Energy-efficiency is crucial for modern radio-frequency (RF) receivers dedicated to Internet of Things applications. Energy-efficiency enhancements could be achieved by lowering the power consumption of integrated circuits, using antenna diversity or even with an association of both strategies. This paper compares two wideband RF front-end architectures, based on conventional low-noise amplifiers (LNA) and low-noise transconductance amplifiers (LNTA) with N-path filters, operating with three transmission schemes: single antenna, antenna selection and singular value decomposition beamforming. Our results show that the energy-efficiency behavior varies depending on the required communication link conditions, distance between nodes and metrics from the front-end receivers. For short-range scenarios, LNA presents the best performance in terms of energy-efficiency mainly due to its very low power consumption. With the increasing of the communication distance, the very low noise figure provided by N-path LNTA-based architectures outperforms the power consumption issue, yielding higher energy-efficiency for all transmission schemes. In addition, the selected front-end architecture depends on the number of active antennas at the receiver. Hence, we can observe that low noise figure is more important with a few active antennas at the receiver, while low power consumption becomes more important when the number of active RF chains at the receiver increases.

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A Study on the Adaptive RF Front-End for Low Power Consumption ISDB-T Receiver

MILCOM 2007 - IEEE Military Communications Conference ◽

10.1109/milcom.2007.4454885 ◽

2007 ◽

Cited By ~ 2

Author(s):

Soo-hwan Kim ◽

Minoru Okada ◽

Takao Hara ◽

Masato Saito

Keyword(s):

Power Consumption ◽

Low Power ◽

Low Power Consumption ◽

Front End ◽

Rf Front End

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A system-level design method for RF receiver front-end with low power consumption

Analog Integrated Circuits and Signal Processing ◽

10.1007/s10470-021-01879-y ◽

2021 ◽

Author(s):

Ziba Fazel ◽

Mojtaba Atarodi ◽

Sirus Sadughi

Keyword(s):

Power Consumption ◽

Low Power ◽

Design Method ◽

System Level ◽

Low Power Consumption ◽

System Level Design ◽

Rf Receiver ◽

Front End ◽

Level Design

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A Linearity Improvement Front End with Subharmonic Current Commutating Passive Mixer for 2.4 GHz Direct Conversion Receiver in 0.13 μm CMOS Technology

Electronics ◽

10.3390/electronics9091369 ◽

2020 ◽

Vol 9 (9) ◽

pp. 1369

Author(s):

Dongquan Huo ◽

Luhong Mao ◽

Liji Wu ◽

Xiangmin Zhang

Keyword(s):

Power Consumption ◽

Flicker Noise ◽

Analytical Formula ◽

Direct Conversion ◽

Low Noise ◽

Cmos Process ◽

Passive Mixer ◽

Dc Offset ◽

Front End ◽

Rf Front End

Direct conversion receiver (DCR) architecture is a promising candidate in the radio frequency (RF) front end because of its low power consumption, low cost and ease of integration. However, flicker noise and direct current (DC) offset are large issues. Owing to the local oscillator (LO) frequency, which is half of the RF frequency, and the absence of a DC bias current that introduces no flicker noise, the subharmonic passive mixer (SHPM) core topology front end overcomes the shortcoming effectively. When more and more receivers (RX) and transmitters (TX) are integrated into one chip, the linearity of the receiver front end becomes a very important performer that handles the TX and RX feedthrough. Another reason for the requirement of good linearity is the massive electromagnetic interference that exists in the atmosphere. This paper presents a linearity-improved RF front end with a feedforward body bias (FBB) subharmonic mixer core topology that satisfies modern RF front end demands. A novel complementary derivative superposition (DS) method is presented in low noise amplifier (LNA) design to cancel both the third- and second-order nonlinearities. To the best knowledge of the authors, this is the first time FBB technology is used in the SHPM core to improve linearity. A Volterra series is introduced to provide an analytical formula for the FBB of the SHPM core. The design was fabricated in a 0.13 μm complementary metal oxide semiconductor (CMOS) process with a chip area of 750 μm × 1270 μm. At a 2.4 GHz working frequency, the measurement result shows a conversion gain of 36 dB, double side band (DSB) noise figure (NF) of 6.8 dB, third-order intermodulation intercept point (IIP3) of 2 dBm, LO–RF isolation of 90 dB and 0.8 mW DC offset with 14.4 mW power consumption at 1.2 V supply voltage. These results exhibit better LO–RF feedthrough and DC offset, good gain and NF, moderate IIP3 and the highest figure of merit compared to the state-of-the-art publications.

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