Surface-potential-based physical compact model for graphene field effect transistor

2016 ◽  
Vol 120 (8) ◽  
pp. 084509 ◽  
Author(s):  
Lingfei Wang ◽  
Songang Peng ◽  
Wei Wang ◽  
Guangwei Xu ◽  
Zhuoyu Ji ◽  
...  
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

A Large-Signal Monolayer Graphene Field-Effect Transistor Compact Model for RF-Circuit Applications

2017 ◽  
Vol 64 (10) ◽  
pp. 4302-4309 ◽  
Author(s):  
Jorge-Daniel Aguirre-Morales ◽  
Sebastien Fregonese ◽  
Chhandak Mukherjee ◽  
Wei Wei ◽  
Henri Happy ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Monolayer Graphene ◽  
Large Signal ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor ◽  
Rf Circuit

scholarly journals Metal oxide-graphene field-effect transistor: interface trap density extraction model

2016 ◽  
Vol 7 ◽  
pp. 1368-1376 ◽  
Author(s):  
Faraz Najam ◽  
Kah Cheong Lau ◽  
Cheng Siong Lim ◽  
Yun Seop Yu ◽  
Michael Loong Peng Tan
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Current Model ◽  
Drain Current ◽  
Interface Trap ◽  
Accurate Calculation ◽  
Trap Charge ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship I ds–V gs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage C tot–V gs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects

2019 ◽  
Vol 28 (14) ◽  
pp. 1950241
Author(s):  
Sudipta Bardhan ◽  
Manodipan Sahoo ◽  
Hafizur Rahaman
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Bilayer Graphene ◽  
Design Environment ◽  
Surface Potentials ◽  
Graphene Field Effect Transistor ◽  
Dual Gate ◽  
Effect Transistor

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([Formula: see text]), transconductance ([Formula: see text]), gate to drain capacitance ([Formula: see text]) and gate to source capacitance ([Formula: see text]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [Formula: see text] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.

scholarly journals Compact Model for L-Shaped Tunnel Field-Effect Transistor Including the 2D Region

2019 ◽  
Vol 9 (18) ◽  
pp. 3716
Author(s):  
Faraz Najam ◽  
Yun Seop Yu
Keyword(s):  
Electric Field ◽  
Poisson Equation ◽  
Surface Potential ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Subthreshold Region ◽  
Source Current ◽  
Effect Transistor

The L-shaped tunneling field-effect transistor (LTFET) is the only line-tunneling type of TFET to be experimentally demonstrated. To date, there is no literature available on the compact model of LTFET. In this paper, a compact model of LTFET is presented. LTFET has both one-dimensional (1D) and 2D band-to-band tunneling (BTBT) components. The 2D BTBT part dominates in the subthreshold region, whereas the 1D BTBT dominates at higher gate-source biases. The model consists of 1D and 2D BTBT models. The 2D BTBT model is based on the assumption that the electric field originating from the gate and terminating at the source edge is perfectly circular. Tunneling path length is obtained by calculating the distance along an electric field arc that runs from gate to source. The 1D BTBT model is based on a simultaneous solution of the 1D Poisson equation in source and channel regions. Expressions for electric field and potential obtained from integrating the Poisson equation in source and channel regions are solved simultaneously to find the surface potential. Once the surface potential is known, all the other unknown variables, including junction potential and source depletion length, can be calculated. Using the potential profile, tunneling lengths were found for both the source-to-channel BTBT regime, and channel-to-channel BTBT regime. The tunneling lengths were used to calculate the BTBT tunneling rate, and finally, the drain-source current as a function of gate-source, and drain-source bias was calculated. The model results were compared against technology computer-aided design (TCAD) simulation results and were found to be in reasonable agreement for a compact model.

scholarly journals A Physic-Based Explicit Compact Model for Reconfigurable Field-Effect Transistor

IEEE Access ◽  
2021 ◽  
pp. 1-1
Author(s):  
Wangze Ni ◽  
Zhen Dong ◽  
Bairun Huang ◽  
Yichi Zhang ◽  
Zhuojun Chen
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Compact Model ◽  
Effect Transistor
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