scholarly journals GaInSb and GaInAsSb thermophotovoltaic device fabrication and characterization

Author(s):  
C. Hitchcock ◽  
R. Gutmann ◽  
J. Borrego ◽  
H. Ehsani ◽  
I. Bhat ◽  
...  

2011 ◽  
Vol 28 (3) ◽  
pp. 24-30 ◽  
Author(s):  
Uda Hashim ◽  
Nazwa Taib ◽  
Thikra S. Dhahi ◽  
Azizullah Saifullah

PurposeNanobiosensors based on nanogap capacitor are widely used for measuring dielectric properties of DNA, protein and biomolecule. The purpose of this paper is to report on the fabrication and characterization polysilicon nanogap patterning using novelties technique.Design/methodology/approachOverall, the polysilicon nanogap pattern was fabricated based on conventional lithographic techniques. For size expansion technique, by employing simple dry thermal oxidation, the couple of nanogap pattern has been expanded to lowest nanogap value. The progress of nanogap pattern expansion was verified by using scanning electron microscopy (SEM). Conductivity, resistivity, and capacitance test were performed to characterize and to measure electrical behavior of full device fabrication.FindingsSEM characterization emphasis on the expansion of polysilicon nanogap pattern increasing with respect to oxidation time. Electrical characterization shows that nanogap enhanced the sensitivity of the device at the value of nano ampere of current.Originality/valueThese simple least‐cost method does not require complicated nanolithography method of fabrication but still possible to serve as biomolecular junction. This approach can be applied extensively to different design of nanogap structure down to several nanometer levels of dimensions. A method of preparing a nanogap electrode according to the present innovation has an advantage of providing active surface that can be easily modified for immobilizations of biomolecules.



2015 ◽  
Vol 77 (21) ◽  
Author(s):  
Khairil Ezwan Kaharudin ◽  
Fauziyah Salehuddin ◽  
Abdul Hamid Hamidon ◽  
Muhammad Nazirul Ifwat Abd Aziz ◽  
Ibrahim Ahmad

The miniaturization in the size of planar MOSFET device seems to be limited when it reaches to 22nm technology node. In this paper, the vertical double gate architecture of MOSFET device with ultrathin Si- pillar was introduced by keeping both silicon dioxide (SiO2) and polysilicon as the main materials. The proposed MOSFET architecture was known as Ultrathin Pillar Vertical Double Gate (VDG) MOSFET device and it was integrated with polysilicon-on-insulator (PSOI) technology for a superior electrical performance. The virtual device fabrication and characterization were done by using ATHENA and ATLAS modules of SILVACO Internationals. The process parameters of the device were then optimized by utilizing L27 orthogonal array of Taguchi method in order to obtain the highest value of drive current (ION) and the lowest value of leakage current (IOFF). The highest value of ION/IOFF ratio after an optimization approach was observed to be 2.154x 1012.







1997 ◽  
Author(s):  
C. Hitchcock ◽  
R. Gutmann ◽  
J. Borrego ◽  
H. Ehsani ◽  
I. Bhat ◽  
...  




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