Compact dual-mode microstrip bandpass filter based on slotted square patch resonator

Purpose The purpose of this paper is to present the design of a compact microstrip bandpass filter (BPF) in dual-mode configuration loaded with cross-loop and square ring slots on a square patch resonator for C-band applications. Design/methodology/approach In the proposed design, the dual-mode response for the filter is realized with two transmission zeros (TZs) by the insertion of a perturbation element at the diagonal corner of the square patch resonator with orthogonal feed lines. Such TZs at the edges of the passband result in better selectivity for the proposed BPF. Moreover, the cross-loop and square ring slots are etched on a square patch resonator to obtain a miniaturized BPF. Findings The proposed dual-mode microstrip filter fabricated in RT/duroid 6010 substrate using PCB technology has a measured minimum insertion loss of 1.8 dB and return loss better than 24.5 dB with a fractional bandwidth (FBW) of 6.9%. A compact size of 7.35 × 7.35 mm2 is achieved for the slotted patch resonator-based dual-mode BPF at the center frequency of 4.76 GHz. As compared with the conventional square patch resonator, a size reduction of 61% is achieved with the proposed slotted design. The feasibility of the filter design is confirmed by the good agreement between the measured and simulated responses. The performance of the proposed filter structure is compared with other dual-mode filter works. Originality/value In the proposed work, a compact dual-mode BPF is reported with slotted structures. The conventional square patch resonator is deployed with cross-loop and square ring slots to design a dual-mode filter with a square perturbation element at its diagonal corner. The proposed filter exhibits compact size and favorable performance compared to other dual-mode filter works reported in literature. The aforementioned design of the dual-mode BPF at 4.76 GHz is suitable for applications in the lower part of the C-band.

Identification of printed circuit boards mechanical properties using response surface methods

Purpose This study aims to discuss the determination of the unknown in-plane mechanical material properties of printed circuit boards (PCBs) by correlating the results from dynamic testing and finite element (FE) models using the response surface method (RSM). Design/methodology/approach The first 10 resonant frequencies and vibratory mode shapes are measured using modal analysis with hammer testing experiment, and hence, systematically compared with finite element analysis (FEA) results. The RSM is consequently used to minimize the cumulative error between dynamic testing and FEA results by continuously modifying the FE model, to acquire material properties of PCBs. Findings Great agreement is shown when comparing FEA to measurements, the optimum in-plane material properties were identified, and hence, verified. Originality/value This paper used FEA and RSMs along with modal measurements to obtain in-plane material properties of PCBs. The methodology presented here can be easily generalized and repeated for different board designs and configurations.

Improvement of inter layer dielectric crack for LQFP C90FG wafer technology devices in copper wire bonding process

Purpose This paper aims to investigate the root causes of and implement the improvements for the inter layer dielectric (ILD) crack for LQFP C90FG (CMOS90 Floating Gate) wafer technology devices in copper wire bonding process. Design/methodology/approach Failure analysis was conducted including cratering, scanning electron microscopy inspection and focus ion beam cross-section analysis, which showed ILD crack. Root cause investigation of ILD crack rate sudden jumping was carried out with cause-and-effect analysis, which revealed the root cause is shallower lead frame down-set. ILD crack mechanism deep-dive on ILD crack due to shallower lead frame down-set, which revealed the mechanism is lead frame flag floating on heat insert. Further investigation and energy dispersive X-ray analysis found the Cu particles on heat insert is another factor that can result in lead frame flag floating. Findings Lead frame flag floating on heat insert caused by shallower lead frame down-set or foreign matter on heat insert is a critical factor of ILD crack that has never been revealed before. Weak wafer structure strength caused by thinner wafer passivation1 thickness and sharp corner at Metal Trench (compared with the benchmarking fab) are other factors that can impact ILD crack. Originality/value For ILD crack improvement in copper wire bonding, besides the obvious factors such as wafer structure and wire bonding parameters, also should take other factors into consideration including lead frame flag floating on heat insert and heat insert maintenance.

A novel miniaturized Koch-Minkowski hybrid fractal antenna

Purpose Antenna miniaturization, multiband operation and wider operational bandwidth are vital to achieve optimal design for modern wireless communication devices. Using fractal geometries is recognized as one of the most promising solutions to attain these characteristics. The purpose of this paper is to present a unique structure of patch antenna using hybrid fractal technique to enhance the performance characteristics for various wireless applications and to achieve better miniaturization. Design/methodology/approach In this paper, the authors propose a novel hybrid fractal antenna by combining Koch and Minkowski (K-M) fractal geometries. A microstrip patch antenna (MPA) operating at 1.8 GHz is incorporated with a novel K-M hybrid fractal geometry. The proposed fractal antenna is designed and simulated in CST Microwave studio and compared with existing Koch fractal geometry. The prototype for the third iteration of the K-M fractal antenna is then fabricated on FR-4 substrate and tested through vector network analyzer for operating band/voltage standing wave ratio. Findings The third iteration of the proposed K-M fractal geometry results in achieving a 20% size reduction as compared to an ordinary MPA for the same resonant frequency with impedance bandwidth of 16.25 MHz and a directional gain of 6.48 dB, respectively. The operating frequency of MPA also lowers down to 1.44 GHz. Originality/value Further testing for the radiation patterns in an anechoic chamber shows good agreement to those of simulated results.

Influence of selected factors on parameters of a cooling system with a Peltier module and forced air flow

Purpose The purpose of this study is to investigate the validation of the usefulness of cooling systems containing Peltier modules for cooling power devices based on measurements of the influence of selected factors on the value of thermal resistance of such a cooling system. Design/methodology/approach A cooling system containing a heat-sink, a Peltier module and a fan was built by the authors and the measurements of temperatures and thermal resistance in various supply conditions of the Peltier module and the fan were carried out and discussed. Findings Conclusions from the research carried out answer the question if the use of Peltier modules in active cooling systems provides any benefits comparing with cooling systems containing just passive heat-sinks or conventional active heat-sinks constructed of a heat-sink and a fan. Research limitations/implications The research carried out is the preliminary stage to asses if a compact thermal model of the investigated cooling system can be formulated. Originality/value In the paper, the original results of measurements and calculations of parameters of a cooling system containing a Peltier module and an active heat-sink are presented and discussed. An influence of power dissipated in the components of the cooling system on its efficiency is investigated.

Improving the electromagnetic compatibility of electronic products by using response surface methodology and artificial neural network

Purpose The purpose of this study is to use the Taguchi Method for parametric design in the early stages of product development. electromagnetic compatibility (EMC) issues can be considered in the early stages of product design to reduce counter-measure components, product cost and labor consumption increases due to a number of design changes in the R&D cycle and to accelerate the R&D process. Design/methodology/approach The three EMC characteristics, including radiated emission, conducted emission and fast transient impulse immunity of power, are considered response values; control factors are determined with respect to the relevant parameters for printed circuit board and mechanical design of the product and peripheral devices used in conjunction with the product are considered as noise factors. The optimal parameter set is determined by using the principal component gray relational analysis in conjunction with both response surface methodology and artificial neural network. Findings Market specifications and cost of components are considered to propose an optimal parameter design set with the number of grounded screw holes being 14, the size of the shell heat dissipation holes being 3 mm and the arrangement angle of shell heat dissipation holes being 45 degrees, to dispose of 390 O filters on the noise source. Originality/value The optimal parameter set can improve EMC effectively to accommodate the design specifications required by customers and pass test regulations.

On the methodology of calculating volume charge density in a MIFGMOS substrate using Poisson’s equation

Purpose This study aims to present a mathematical method based on Poisson’s equation to calculate the voltage and volume charge density formed in the substrate under the floating gate area of a multiple-input floating-gate metal-oxide semiconductor metal-oxide semiconductor (MOS) transistor. Design/methodology/approach Based on this method, the authors calculate electric fields and electric potentials from the charges generated when voltages are applied to the control gates (CG). This technique allows us to consider cases when the floating gate has any trapped charge generated during the manufacturing process. Moreover, the authors introduce a mathematical function to describe the potential behavior through the substrate. From the resultant electric field, the authors compute the volume charge density at different depths. Findings The authors generate some three-dimensional graphics to show the volume charge density behavior, which allows us to predict regions in which the volume charge density tends to increase. This will be determined by the voltages on terminals, which reveal the relationship between CG and volume charge density and will allow us to analyze some superior-order phenomena. Originality/value The procedure presented here and based on coordinates has not been reported before, and it is an aid to generate a model of the device and to build simulation tools in an analog design environment.

Optimization of flexible printed circuit board’s cooling with air flow and thermal effects using response surface methodology

Purpose This study aims to investigate the interaction of independent variables [Reynolds number (Re), thermal power and the number of ball grid array (BGA) packages] and the relation of the variables with the responses [Nusselt number ((Nu) ¯ ), deflection/FPCB’s length (d/L) and von Mises stress]. The airflow and thermal effects were considered for optimizing the Re of various numbers of BGA packages with thermal power attached on flexible printed circuit board (FPCB) for optimum cooling performance with least deflection and stress by using the response surface method (RSM). Design/methodology/approach Flow and thermal effects on FPCB with heat source generated in the BGA packages have been examined in the simulation. The interactive relationship between factors (i.e. Re, thermal power and number of BGA packages) and responses (i.e. deflection over FPCB length ratio, stress and average Nusselt number) were analysed using analysis of variance. RSM was used to optimize the Re for the different number of BGA packages attached to the FPCB. Findings It is important to understand the behaviour of FPCB when exposed to both flow and thermal effects simultaneously under the operating conditions. Maximum d/L and von Misses stress were significantly affected by all parametric factors whilst (Nu)¯ is significantly affected by Re and thermal power. Optimized Re for 1–3 BGA packages with maximum thermal power applied has been identified as 21,364, 23,858 and 29,367, respectively. Practical implications This analysis offers a better interpretation of the parameter control in FPCB with optimized Re for the use of force convection electronic cooling. Optimal Re could be used as a reference in the thermal management aspect in designing the BGA package. Originality/value This research presents the parameters’ effects on the reliability and heat transfer in FPCB design. It also presents a method to optimize Re for the different number of BGA packages attached to increase the reliability in FPCB’s design.

Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

Computer‐aided selective production of low-resistance NiP and NiCuP layers

Purpose This paper aims to present the possibility of computer-aided technology of chemical metallization for the production of electrodes and resistors based on Ni-P and Ni-Cu-P layers. Design/methodology/approach Based on the calculated parameters of the process, test structures were made on an alumina substrate using the selective metallization method. Dependences of the surface resistance on the metallization time were made. These dependencies take into account the comparison of the calculations with the performed experiment. Findings The author created a convenient and easy-to-use tool for calculating basic Ni-P and Ni-Cu-P layer parameters, namely, surface resistance and temperature coefficient of resistance (TCR) of test resistor, based on chemical metallization parameters. The values are calculated for a given level of surface resistance of Ni-P and Ni-Cu-P layer and defined required range of changes of TCR of test resistor. The calculations are possible for surface resistance values in the range of 0.4 Ohm/square ÷ 2.5 Ohm/square. As a result of the experiment, surface resistances were obtained that practically coincide with the calculations made with the use of the program created by the authors. The quality of the structures made is very good. Originality/value To the best of the authors’ knowledge, the paper presents a new, unpublished method of manufacturing electrodes (resistors) on silicon, Al2O3 and low temperature co-fired ceramic substrates based on the authors developed computer program.