Commutative encryption based video encoding technique with high-efficiency & video adaptation capabilities

2021 ◽  
Vol 24 (8) ◽  
pp. 2207-2219
Author(s):  
Himanshu Sharma ◽  
Rajneesh Pareek ◽  
Ashutosh Kumar ◽  
Nidhi Gour ◽  
Ravi Shanker Sharma ◽  
...  
Keyword(s):  
High Efficiency ◽  
Video Encoding ◽  
Video Adaptation

scholarly journals H.265 Intra-Picture Prediction Acceleration using Low Complexity Model

2019 ◽  
Vol 8 (11) ◽  
pp. 2939-2944
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Low Complexity ◽  
Video Encoding ◽  
High Efficiency Video Coding ◽  
Tree Model ◽  
Time Saving ◽  
Applied Machine Learning ◽  
Additional Burden ◽  
Increasing Demand

H.265 also called High Efficiency Video Coding is the new futuristic international standard proposed by Joint collaboration Team on Video Coding and released in 2013 in the view of constantly increasing demand of video applications. This new standard reduces the bitrate to half as compared to its predecessor H.264 at the expense of huge amount of computational burden on the encoder. In the proposed work we focus on intraprediction phase of video encoding where 33 new angular modes are introduced in addition to DC and Planar mode in order to achieve high quality videos at higher resolutions. We have proposed the use of applied machine learning to HEVC intra prediction to accelerate angular mode decision process. The features used are also low complexity features with minimal computation so as to avoid any additional burden on the encoder. The Decision tree model built is simple yet efficient which is the requirement of the complexity reduction scenario. The proposed method achieves substantial average encoding time saving of 86.59%, with QP values 4,22,27,32 respectively with minimal loss of 0.033 of PSNR and 0.0023 loss in SSIM which makes it suitable for acceptance of High Efficiency Video coding in real time applications

scholarly journals High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

2019 ◽  
Vol 8 (6) ◽  
pp. 1235-1238
Keyword(s):  
Motion Estimation ◽  
Video Compression ◽  
High Speed ◽  
High Performance ◽  
High Efficiency ◽  
Block Size ◽  
Video Encoding ◽  
Computational Time ◽  
Absolute Difference ◽  
Asymmetric Mode

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures.

scholarly journals Encryption for high efficiency video coding with video adaptation capabilities

2013 ◽  
Vol 59 (3) ◽  
pp. 634-642 ◽  
Author(s):  
Glenn Van Wallendael ◽  
Andras Boho ◽  
Jan De Cock ◽  
Adrian Munteanu ◽  
Rik Van De Walle
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Video Adaptation ◽  
High Efficiency Video Coding

A New Fast Algorithm for Intra Prediction Mode Selection in the High Efficiency Video Coding (HEVC) Standard

2014 ◽  
Vol 926-930 ◽  
pp. 3342-3345
Author(s):  
Chun Jiang Duanmu ◽  
Duo Dong ◽  
Xu Qiang Yang
Keyword(s):  
High Efficiency ◽  
Mode Selection ◽  
Intra Prediction ◽  
Code Rate ◽  
Video Encoding ◽  
Expert Group ◽  
High Efficiency Video Coding ◽  
Video Information ◽  
Prediction Mode ◽  
Very High

In order to meet the trend and consumer demands for video information, the ISO/IEC group and ITU-T video encoding expert group have cooperated in making the new video encoding standard of HEVC. It defines 35 Intra prediction modes and thus has a very high encoding complexity. In order to reduce this complexity, this paper has proposed a new algorithm to effectively reduce the number of the candidate mode which needs to be checked. The edge detection and Hough transform are utilized for the prediction unit (PU) with different sizes. Statistical analysis is utilized for the detected edge line angles to decide the candidate modes that need to be checked. The C++ and OpenCV language have been utilized for the implementation of the proposed algorithm. The proposed algorithm can reduce the encoding time by 43.72 percent at most and 17.06 percent at least with just little increase of the code rate and small decrease of the PSNR.

scholarly journals Steganography algorithm based on modified EMD coded PU partition modes for HEVC videos

2021 ◽  
Author(s):  
Zhenzhen Zhang ◽  
Zhaohong Li ◽  
Jindou Liu ◽  
Huanma Yan ◽  
Lifang Yu
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
State Of The Art ◽  
Visual Quality ◽  
Video Encoding ◽  
Embedding Capacity ◽  
High Efficiency Video Coding ◽  
Exploiting Modification Direction ◽  
The One ◽  
Notational System

Abstract As High Efficiency Video Coding (HEVC) is a worldwide popular video coding standard, the steganography of HEVC videos has gained more and more attention. Prediction Unit (PU) is one of the most important innovative modules of HEVC, thus PU partition mode based steganography is becoming a novel branch of HEVC steganography. However, the embedding capacity of this kind of steganography is limited by the types of PU partition modes. To solve the problem, modified Exploiting Modification Direction (EMD) coded PU partition modes based steganography is proposed in this paper, which can hide a secret digit in a ( [[EQUATION]] )-ary notational system in a pair of PU partition modes and thus enlarging the capacity. Furthermore, two mapping patterns for PU partition modes are analyzed and the one that performs the better is selected as the final mapping pattern. Firstly, 8×8 and 16×16 sized PU partition modes are recorded according to the optimal mapping pattern in the video encoding process. Then PU partition modes are modified by using the proposed method to satisfy the requirement of secret information. Finally, the stego video can be obtained by re-encoding the video with the modified PU partition modes. Experimental results show that the embedding capacity can be significantly enlarged, and compared with the state-of-the-art work, the proposed method has much larger capacity while keeping high visual quality.

scholarly journals Exploring Absolute Differences Arithmetic Operators for Power and Area-Efficient SAD Hardware Architectures

2020 ◽  
Vol 15 (1) ◽  
pp. 1-9
Author(s):  
Brunno Alves Abreu ◽  
Mateus Grellert ◽  
Guilherme Paim ◽  
Leandro Mateus Giacomini Rocha ◽  
Cláudio Machado Diniz ◽  
...  
Keyword(s):  
High Efficiency ◽  
Cmos Technology ◽  
Video Encoding ◽  
High Efficiency Video Coding ◽  
Power Efficient ◽  
Input Size ◽  
Important Research Topic ◽  
Synthesis Tool ◽  
Hardware Architectures ◽  
The Impact

Managing the energy requirements of video encoders has been an important research topic throughout the latest years, given the limited resources of battery-powered systems. Sum of Absolute Differences (SAD) stands out among the most costly steps in the video encoding process compliant with the High Efficiency Video Coding (HEVC) standard. This metric is mainly used to explore temporal redundancies during the inter prediction stage of the encoder, and it is applied by adding the absolute differences of the colocalized pixels of two video blocks, as a means of measuring the similarity between them. SAD architectures are usually designed by using an adder tree, with its first level consisting of subtractors and absolute operators. This paper explores various structures of absolute operators in the context of SAD architectures, in order to define the most suitable implementation for a power-efficient SAD module. Besides the analysis of several different models, we exploit the use of pipelining, and the impact of varying block input bitwidth, to determine which versions scale better with the increase of input size. We have synthesized the architectures for ASIC CMOS technology using real-input vectors taking the delays into consideration, with an ST 65 nm standard cells library, and compared them with the default absolute operator macrofunction from the synthesis tool.

scholarly journals Steganography algorithm based on modified EMD coded PU partition modes for HEVC videos

2020 ◽  
Author(s):  
Zhenzhen Zhang ◽  
Zhaohong Li ◽  
Jindou Liu ◽  
Huanma Yan
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
State Of The Art ◽  
Visual Quality ◽  
Video Encoding ◽  
Embedding Capacity ◽  
High Efficiency Video Coding ◽  
Exploiting Modification Direction ◽  
The One ◽  
Notational System

Abstract As High Efficiency Video Coding (HEVC) is a worldwide popular video coding standard, the steganography of HEVC videos has gained more and more attention. Prediction Unit (PU) is one of the most important innovative modules of HEVC, thus PU partition mode based steganography is becoming a novel branch of HEVC steganography. However, the embedding capacity of this kind of steganography is limited by the types of PU partition modes. To solve the problem, modified Exploiting Modification Direction (EMD) coded PU partition modes based steganography is proposed in this paper, which can hide a secret digit in a (\({2^{n+x}} - 1\))-ary notational system in a pair of PU partition modes and thus enlarging the capacity. Furthermore, two mapping patterns for PU partition modes are analyzed and the one that performs the better is selected as the final mapping pattern. Firstly, 8 × 8 and 16 × 16 sized PU partition modes are recorded according to the optimal mapping pattern in the video encoding process. Then PU partition modes are modified by using the proposed method to satisfy the requirement of secret information. Finally, the stego video can be obtained by re-encoding the video with the modified PU partition modes. Experimental results show that the embedding capacity can be significantly enlarged, and compared with the state-of-the-art work, the proposed method has much larger capacity while keeping high visual quality.

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