scholarly journals Exploring Absolute Differences Arithmetic Operators for Power and Area-Efficient SAD Hardware Architectures

2020 ◽  
Vol 15 (1) ◽  
pp. 1-9
Author(s):  
Brunno Alves Abreu ◽  
Mateus Grellert ◽  
Guilherme Paim ◽  
Leandro Mateus Giacomini Rocha ◽  
Cláudio Machado Diniz ◽  
...  
Keyword(s):  
High Efficiency ◽  
Cmos Technology ◽  
Video Encoding ◽  
High Efficiency Video Coding ◽  
Power Efficient ◽  
Input Size ◽  
Important Research Topic ◽  
Synthesis Tool ◽  
Hardware Architectures ◽  
The Impact

Managing the energy requirements of video encoders has been an important research topic throughout the latest years, given the limited resources of battery-powered systems. Sum of Absolute Differences (SAD) stands out among the most costly steps in the video encoding process compliant with the High Efficiency Video Coding (HEVC) standard. This metric is mainly used to explore temporal redundancies during the inter prediction stage of the encoder, and it is applied by adding the absolute differences of the colocalized pixels of two video blocks, as a means of measuring the similarity between them. SAD architectures are usually designed by using an adder tree, with its first level consisting of subtractors and absolute operators. This paper explores various structures of absolute operators in the context of SAD architectures, in order to define the most suitable implementation for a power-efficient SAD module. Besides the analysis of several different models, we exploit the use of pipelining, and the impact of varying block input bitwidth, to determine which versions scale better with the increase of input size. We have synthesized the architectures for ASIC CMOS technology using real-input vectors taking the delays into consideration, with an ST 65 nm standard cells library, and compared them with the default absolute operator macrofunction from the synthesis tool.

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

scholarly journals Low delay error resilience algorithm for H.265|HEVC video transmission

2019 ◽  
Vol 17 (6) ◽  
pp. 2047-2063
Author(s):  
Taha T. Alfaqheri ◽  
Abdul Hamid Sadka
Keyword(s):  
Video Coding ◽  
Video Transmission ◽  
High Efficiency ◽  
Video Quality ◽  
Error Resilience ◽  
Video Codec ◽  
Compressed Video ◽  
High Efficiency Video Coding ◽  
Low Delay ◽  
The Impact

AbstractTransmission of high-resolution compressed video on unreliable transmission channels with time-varying characteristics such as wireless channels can adversely affect the decoded visual quality at the decoder side. This task becomes more challenging when the video codec computational complexity is an essential factor for low delay video transmission. High-efficiency video coding (H.265|HEVC) standard is the most recent video coding standard produced by ITU-T and ISO/IEC organisations. In this paper, a robust error resilience algorithm is proposed to reduce the impact of erroneous H.265|HEVC bitstream on the perceptual video quality at the decoder side. The proposed work takes into consideration the compatibility of the algorithm implementations with and without feedback channel update. The proposed work identifies and locates the frame’s most sensitive areas to errors and encodes them in intra mode. The intra-refresh map is generated at the encoder by utilising a grey projection method. The conducted experimental work includes testing the codec performance with the proposed work in error-free and error-prone conditions. The simulation results demonstrate that the proposed algorithm works effectively at high packet loss rates. These results come at the cost of a slight increase in the encoding bit rate overhead and computational processing time compared with the default HEVC HM16 reference software.

scholarly journals H.265 Intra-Picture Prediction Acceleration using Low Complexity Model

2019 ◽  
Vol 8 (11) ◽  
pp. 2939-2944
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Low Complexity ◽  
Video Encoding ◽  
High Efficiency Video Coding ◽  
Tree Model ◽  
Time Saving ◽  
Applied Machine Learning ◽  
Additional Burden ◽  
Increasing Demand

H.265 also called High Efficiency Video Coding is the new futuristic international standard proposed by Joint collaboration Team on Video Coding and released in 2013 in the view of constantly increasing demand of video applications. This new standard reduces the bitrate to half as compared to its predecessor H.264 at the expense of huge amount of computational burden on the encoder. In the proposed work we focus on intraprediction phase of video encoding where 33 new angular modes are introduced in addition to DC and Planar mode in order to achieve high quality videos at higher resolutions. We have proposed the use of applied machine learning to HEVC intra prediction to accelerate angular mode decision process. The features used are also low complexity features with minimal computation so as to avoid any additional burden on the encoder. The Decision tree model built is simple yet efficient which is the requirement of the complexity reduction scenario. The proposed method achieves substantial average encoding time saving of 86.59%, with QP values 4,22,27,32 respectively with minimal loss of 0.033 of PSNR and 0.0023 loss in SSIM which makes it suitable for acceptance of High Efficiency Video coding in real time applications

scholarly journals FPGA-based implementation of intra prediction module for HEVC decoder

2019 ◽  
Vol 8 (2) ◽  
pp. 6130-6137
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Cmos Technology ◽  
Intra Prediction ◽  
Hardware Architecture ◽  
Video Frame ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Prediction Module ◽  
Block Sizes

The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.

A New Fast Algorithm for Intra Prediction Mode Selection in the High Efficiency Video Coding (HEVC) Standard

2014 ◽  
Vol 926-930 ◽  
pp. 3342-3345
Author(s):  
Chun Jiang Duanmu ◽  
Duo Dong ◽  
Xu Qiang Yang
Keyword(s):  
High Efficiency ◽  
Mode Selection ◽  
Intra Prediction ◽  
Code Rate ◽  
Video Encoding ◽  
Expert Group ◽  
High Efficiency Video Coding ◽  
Video Information ◽  
Prediction Mode ◽  
Very High

In order to meet the trend and consumer demands for video information, the ISO/IEC group and ITU-T video encoding expert group have cooperated in making the new video encoding standard of HEVC. It defines 35 Intra prediction modes and thus has a very high encoding complexity. In order to reduce this complexity, this paper has proposed a new algorithm to effectively reduce the number of the candidate mode which needs to be checked. The edge detection and Hough transform are utilized for the prediction unit (PU) with different sizes. Statistical analysis is utilized for the detected edge line angles to decide the candidate modes that need to be checked. The C++ and OpenCV language have been utilized for the implementation of the proposed algorithm. The proposed algorithm can reduce the encoding time by 43.72 percent at most and 17.06 percent at least with just little increase of the code rate and small decrease of the PSNR.

scholarly journals Modern Video Coding: Methods, Challenges and Systems

2021 ◽  
Vol 16 (2) ◽  
pp. 1-12
Author(s):  
Roberta De Carvalho Nobre Palau ◽  
Bianca Santos da Cunha Silveira ◽  
Robson André Domanski ◽  
Marta Breunig Loose ◽  
Arthur Alves Cerveira ◽  
...  
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
High Efficiency ◽  
High Efficiency Video Coding ◽  
Ultrahigh Resolution ◽  
Daily Lives ◽  
Open Research ◽  
Hardware Architectures ◽  
Increasing Demand ◽  
Dedicated Hardware

With the increasing demand for digital video applications in our daily lives, video coding and decoding become critical tasks that must be supported by several types of devices and systems. This paper presents a discussion of the main challenges to design dedicated hardware architectures based on modern hybrid video coding formats, such as the High Efficiency Video Coding (HEVC), the AOMedia Video 1 (AV1) and the Versatile Video Coding (VVC). The paper discusses eachstep of the hybrid video coding process, highlighting the main challenges for each codec and discussing the main hardware solutions published in the literature. The discussions presented in the paper show that there are still many challenges to be overcome and open research opportunities, especially for the AV1 and VVC codecs. Most of these challenges are related to the high throughput required for processing high and ultrahigh resolution videos in real time and to energy constraints of multimedia-capable devices.

scholarly journals Steganography algorithm based on modified EMD coded PU partition modes for HEVC videos

2021 ◽  
Author(s):  
Zhenzhen Zhang ◽  
Zhaohong Li ◽  
Jindou Liu ◽  
Huanma Yan ◽  
Lifang Yu
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
State Of The Art ◽  
Visual Quality ◽  
Video Encoding ◽  
Embedding Capacity ◽  
High Efficiency Video Coding ◽  
Exploiting Modification Direction ◽  
The One ◽  
Notational System

Abstract As High Efficiency Video Coding (HEVC) is a worldwide popular video coding standard, the steganography of HEVC videos has gained more and more attention. Prediction Unit (PU) is one of the most important innovative modules of HEVC, thus PU partition mode based steganography is becoming a novel branch of HEVC steganography. However, the embedding capacity of this kind of steganography is limited by the types of PU partition modes. To solve the problem, modified Exploiting Modification Direction (EMD) coded PU partition modes based steganography is proposed in this paper, which can hide a secret digit in a ( [[EQUATION]] )-ary notational system in a pair of PU partition modes and thus enlarging the capacity. Furthermore, two mapping patterns for PU partition modes are analyzed and the one that performs the better is selected as the final mapping pattern. Firstly, 8×8 and 16×16 sized PU partition modes are recorded according to the optimal mapping pattern in the video encoding process. Then PU partition modes are modified by using the proposed method to satisfy the requirement of secret information. Finally, the stego video can be obtained by re-encoding the video with the modified PU partition modes. Experimental results show that the embedding capacity can be significantly enlarged, and compared with the state-of-the-art work, the proposed method has much larger capacity while keeping high visual quality.

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