scholarly journals The Single Row Routing Problem Revisited: A Solution Based on Genetic Algorithms

VLSI Design ◽  
2002 ◽  
Vol 14 (2) ◽  
pp. 123-141 ◽  
Author(s):  
Albert Y. Zomaya ◽  
Roger Karpin ◽  
Stephan Olariu
Keyword(s):  
Genetic Algorithms ◽  
Computer Aided Design ◽  
High Performance ◽  
Printed Circuit Boards ◽  
Heuristic Algorithms ◽  
Classical Problem ◽  
Vlsi Circuits ◽  
Single Chip ◽  
Routing Problem ◽  
Single Row

With the advent of VLSI technology, circuits with more than one million transistors have been integrated onto a single chip. As the complexity of ICs grows, the time and money spent on designing the circuits become more important. A large, often dominant, part of the cost and time required to design an IC is consumed in the routing operation. The routing of carriers, such as in IC chips and printed circuit boards, is a classical problem in Computer Aided Design. With the complexity inherent in VLSI circuits, high performance routers are necessary. In this paper, a crucial step in the channel routing technique, the single row routing (SRR) problem, is considered. First, we discuss the relevance of SRR in the context of the general routing problem. Secondly, we show that heuristic algorithms are far from solving the general problem. Next, we introduce evolutionary computation, and, in particular, genetic algorithms (GAs) as a justifiable method in solving the SRR problem. Finally, an efficient O (nk) complexity technique based on GAs heuristic is obtained to solve the general SRR problem containing n nodes. Experimental results show that the algorithm is faster and can often generate better results than many of the leading heuristics proposed in the literature.

Wire length optimization of VLSI circuits using IWO algorithm and its hybrid

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Subhrapratim Nath ◽  
Jamuna Kanta Sing ◽  
Subir Kumar Sarkar
Keyword(s):  
Circuit Design ◽  
Heuristic Algorithms ◽  
Vlsi Circuits ◽  
Global Routing ◽  
Vlsi Circuit ◽  
Wire Length ◽  
Invasive Weed ◽  
Routing Problem ◽  
Content Type ◽  
Rectilinear Steiner Tree

Purpose Advancement in optimization of VLSI circuits involves reduction in chip size from micrometer to nanometer level as well as fabrication of a billions of transistors in a single die where global routing problem remains significant with a trade-off of power dissipation and interconnect delay. This paper aims to solve the increased complexity in VLSI chip by minimization of the wire length in VLSI circuits using a new approach based on nature-inspired meta-heuristic, invasive weed optimization (IWO). Further, this paper aims to achieve maximum circuit optimization using IWO hybridized with particle swarm optimization (PSO). Design/methodology/approach This paper projects the complexities of global routing process of VLSI circuit design in mapping it with a well-known NP-complete problem, the minimum rectilinear Steiner tree (MRST) problem. IWO meta-heuristic algorithm is proposed to meet the MRST problem more efficiently and thereby reducing the overall wire-length of interconnected nodes. Further, the proposed approach is hybridized with PSO, and a comparative analysis is performed with geosteiner 5.0.1 and existing PSO technique over minimization, consistency and convergence against available benchmark. Findings This paper provides high performance–enhanced IWO algorithm, which keeps in generating low MRST value, thereby successful wire length reduction of VLSI circuits is significantly achieved as evident from the experimental results as compared to PSO algorithm and also generates value nearer to geosteiner 5.0.1 benchmark. Even with big VLSI instances, hybrid IWO with PSO establishes its robustness over achieving improved optimization of overall wire length of VLSI circuits. Practical implications This paper includes implications in the areas of optimization of VLSI circuit design specifically in the arena of VLSI routing and the recent developments in routing optimization using meta-heuristic algorithms. Originality/value This paper fulfills an identified need to study optimization of VLSI circuits where minimization of overall interconnected wire length in global routing plays a significant role. Use of nature-based meta-heuristics in solving the global routing problem is projected to be an alternative approach other than conventional method.

A PARALLEL ALGORITHM FOR SINGLE ROW ROUTING PROBLEMS

1992 ◽  
Vol 02 (02) ◽  
pp. 113-139
Author(s):  
ARNOB ROY ◽  
JITENDER DEOGUN ◽  
NAVEED A. SHERWANI
Keyword(s):  
Parallel Algorithm ◽  
Printed Circuit Boards ◽  
Sequential Algorithm ◽  
Circuit Boards ◽  
Sequential Algorithms ◽  
Routing Problems ◽  
Routing Problem ◽  
Single Row ◽  
Decomposition Scheme ◽  
Speed Up

Single Row Routing problem is one of the important subproblems in the layout design of multilayer printed circuit boards. This routing technique has also been applied to routing of microwave citcuits and other routing problems. The single row routing problem has been extensively studied and several sequential algorithms have been proposed. In this paper, we present a parallel hypercube algorithm for the single row routing problem. The basis of this parallel algorithm is a new O(n2 log n) sequential algorithm based on the concept of modified cut numbers and a graph decomposition scheme. The sequential algorithm is based on generalizing the concepts underlying two existing sequential algorithms. A parallel algorithm for the hypercube architecture with N processors is then developed by combining the nice features of the sequential algorithm with an efficient allocation scheme. This results in a parallel algorithm of [Formula: see text] complexity. The experimental results show that our algorithm achieves a speed up factor that is quite close to the theoretical bound while maintaining the quality of the solutions, as compared to any existing sequential algorithm. Moreover, the algorithm produces 28% better results than any existing results.

DESIGN OF HIGH PERFORMANCE PULSE GENERATOR TO PERFORM AUTOMATIC TEST IN VLSI CIRCUITS

2019 ◽  
Vol 9 (3) ◽  
pp. 26
Author(s):  
P. LOKESH ◽  
V. THRIMURTHULU ◽  
PRIYA L. MIHIRA ◽  
◽  
◽  
...  
Keyword(s):  
High Performance ◽  
Pulse Generator ◽  
Vlsi Circuits ◽  
Automatic Test

Hydrodynamic Design System for Pumps Based on 3-D CAD, CFD, and Inverse Design Method

2002 ◽  
Vol 124 (2) ◽  
pp. 329-335 ◽  
Author(s):  
Akira Goto ◽  
Motohiko Nohmi ◽  
Takaki Sakurai ◽  
Yoshiyasu Sogawa
Keyword(s):  
Computer Aided Design ◽  
High Performance ◽  
Design Method ◽  
High Reliability ◽  
Secondary Flows ◽  
System Structure ◽  
Inverse Design ◽  
Design System ◽  
Centrifugal Impeller ◽  
Inverse Design Method

A computer-aided design system has been developed for hydraulic parts of pumps including impellers, bowl diffusers, volutes, and vaned return channels. The key technologies include three-dimensional (3-D) CAD modeling, automatic grid generation, CFD analysis, and a 3-D inverse design method. The design system is directly connected to a rapid prototyping production system and a flexible manufacturing system composed of a group of DNC machines. The use of this novel design system leads to a drastic reduction of the development time of pumps having high performance, high reliability, and innovative design concepts. The system structure and the design process of “Blade Design System” and “Channel Design System” are presented. Then the design examples are presented briefly based on the previous publications, which included a centrifugal impeller with suppressed secondary flows, a bowl diffuser with suppressed corner separation, a vaned return channel of a multistage pump, and a volute casing. The results of experimental validation, including flow fields measurements, were also presented and discussed briefly.

scholarly journals A Deep Reinforcement Learning Approach for Global Routing

2019 ◽  
Vol 142 (6) ◽  
Author(s):  
Haiguang Liao ◽  
Wentai Zhang ◽  
Xuliang Dong ◽  
Barnabas Poczos ◽  
Kenji Shimada ◽  
...  
Keyword(s):  
Reinforcement Learning ◽  
Integrated Circuits ◽  
Printed Circuit Boards ◽  
Greedy Algorithms ◽  
Global Routing ◽  
Hydraulic Systems ◽  
Routing Problem ◽  
Future Data ◽  
Circuit Components ◽  
Optimization Mechanism

Abstract Global routing has been a historically challenging problem in the electronic circuit design, where the challenge is to connect a large and arbitrary number of circuit components with wires without violating the design rules for the printed circuit boards or integrated circuits. Similar routing problems also exist in the design of complex hydraulic systems, pipe systems, and logistic networks. Existing solutions typically consist of greedy algorithms and hard-coded heuristics. As such, existing approaches suffer from a lack of model flexibility and usually fail to solve sub-problems conjointly. As an alternative approach, this work presents a deep reinforcement learning method for solving the global routing problem in a simulated environment. At the heart of the proposed method is deep reinforcement learning that enables an agent to produce a policy for routing based on the variety of problems, and it is presented with leveraging the conjoint optimization mechanism of deep reinforcement learning. Conjoint optimization mechanism is explained and demonstrated in detail; the best network structure and the parameters of the learned model are explored. Based on the fine-tuned model, routing solutions and rewards are presented and analyzed. The results indicate that the approach can outperform the benchmark method of a sequential A* method, suggesting a promising potential for deep reinforcement learning for global routing and other routing or path planning problems in general. Another major contribution of this work is the development of a global routing problem sets generator with the ability to generate parameterized global routing problem sets with different size and constraints, enabling evaluation of different routing algorithms and the generation of training datasets for future data-driven routing approaches.

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