Ge 1 Sb 2 Te 4 Based Chalcogenide Random Access Memory Array Fabricated by 0.18-μm CMOS Technology

2007 ◽  
Vol 24 (3) ◽  
pp. 790-792 ◽  
Author(s):  
Zhang Ting ◽  
Song Zhi-Tang ◽  
Feng Gao-Ming ◽  
Liu Bo ◽  
Wu Liang-Cai ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Cmos Technology ◽  
Access Memory ◽  
Memory Array

A SPICE Model of Resistive Random Access Memory for Large-Scale Memory Array Simulation

2014 ◽  
Vol 35 (2) ◽  
pp. 211-213 ◽  
Author(s):  
Haitong Li ◽  
Peng Huang ◽  
Bin Gao ◽  
Bing Chen ◽  
Xiaoyan Liu ◽  
...  
Keyword(s):  
Large Scale ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Memory Array ◽  
Spice Model

scholarly journals Highly Reliable Memory Operation of High Density Three-Terminal Thyristor Random Access Memory

2021 ◽  
Author(s):  
Hyangwoo Kim ◽  
Hyeonsu Cho ◽  
Hyeon-Tak Kwak ◽  
Myunghae Seo ◽  
Seungho Lee ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
High Density ◽  
Data Retention ◽  
Access Memory ◽  
Cathode Voltage ◽  
Cross Point ◽  
Memory Array ◽  
Retention Characteristics ◽  
Power Operation

Abstract Three-terminal (3-T) thyristor random-access memory is explored for a next generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate-cathode voltage (VGC,ST) and anode- cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of -0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate-cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.

scholarly journals Stateful Logic Operations in One-Transistor-One- Resistor Resistive Random Access Memory Array

2019 ◽  
Vol 40 (9) ◽  
pp. 1538-1541 ◽  
Author(s):  
Wensheng Shen ◽  
Peng Huang ◽  
Mengqi Fan ◽  
Runze Han ◽  
Zheng Zhou ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Memory Array ◽  
Logic Operations

Optimal design of phase change random access memory based on 130nm CMOS technology

2013 ◽  
Author(s):  
Daolin Cai ◽  
Houpeng Chen ◽  
Qian Wang ◽  
Xiao Hong ◽  
Yifeng Chen ◽  
...  
Keyword(s):  
Optimal Design ◽  
Phase Change ◽  
Random Access ◽  
Random Access Memory ◽  
Cmos Technology ◽  
Access Memory

Suppression of relaxation effect in HfO2resistive random access memory array by improved program operations

2016 ◽  
Vol 9 (5) ◽  
pp. 051501
Author(s):  
Chen Wang ◽  
Huaqiang Wu ◽  
Bin Gao ◽  
Lingjun Dai ◽  
Ning Deng ◽  
...  
Keyword(s):  
Random Access ◽  
Random Access Memory ◽  
Relaxation Effect ◽  
Access Memory ◽  
Memory Array

Multiple phase change structure for the scalable phase change random access memory array

2014 ◽  
Vol 53 (4) ◽  
pp. 041801
Author(s):  
Jung-Min Lee ◽  
Yuta Saito ◽  
Yuji Sutou ◽  
Junichi Koike ◽  
Jin Won Jung ◽  
...  
Keyword(s):  
Phase Change ◽  
Random Access ◽  
Random Access Memory ◽  
Access Memory ◽  
Memory Array ◽  
Multiple Phase
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