Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

The Effect of Grain Boundary on Electrical Characteristics in the Source and Drain Regions of Polycrystalline Silicon Based in One Transistor Dynamic Random Access Memory

In this paper, we present a capacitorless one transistor dynamic random access memory (1T-DRAM) based on a polycrystalline silicon (poly-Si) double gate MOSFET with grain boundaries (GBs). Several studies have been conducted to implement 1T-DRAM using poly-Si. This is because poly-Si has the advantage of low-cost fabrication and can be stacked. However, poly-Si has GBs, which can adversely affect semiconductor device. So far, related studies on poly-Si-based 1T-DRAM have only focused on GBs present in the channel domain. Hence, in this study, we analyzed the transfer and memory characteristics when a GB is present in the source and drain regions. As a result, we found that in the center of the depletion region in the source and channel junction, where the effect of GB was most significant, sensing margins decreased the most from 0.88 to 0.29 μA/μm, and retention time (RT) decreased from 85 ms to 47 μs. In addition, we found that at the center of the depletion region in the drain and channel junction, where the effect of GBs was most significant in the drain region, RT decreased the most from 85 ms to 52 μs.

Design of Dynamic Random Access Memory Based on One Transistor One Diode Memory Cell

This paper presents the design analysis of Dynamic Random Access Memory (DRAM) with one transistor one diode (1T1D). The proposed structure consists of one transistor and one voltage controlled diode capacitor. The word and bit lines are connected with two voltage sources for the write operation. The source and drain of the NMOS is tied together to form the diode structure. The off-state leakage current is the main cause for the power dissipation of DRAM. Thus the improvement of power efficiency to the overall system is a critical task. The conventional DRAM cell contains one capacitor and one transistor. But the absence of capacitor in the proposed work is advantageous by means of compatibility, scalability, fabrication complexity, and cost. Tanner EDA working platform of 7 nm technology is used for the implementation of 1T1D DRAM cell in proposed work. This work achieve the power dissipation, read and write access time in the range of 2.647 mW, 0.04 μs and 0.021 μs respectively. Also, the parameter comparison is performed by changing the technologies from 10 nm to 20 nm for 1T1D DRAM cell design.

Partial Isolation Type Buried Channel Array Transistor (Pi-BCAT) for a Sub-20 nm DRAM Cell Transistor

In this paper, we propose a new buried channel array transistor structure to solve the problem of current leakage occurring in the capacitors of dynamic random-access memory (DRAM) cells. This structure has a superior off current performance compared with three previous types of structures. In particular, the proposed buried channel array transistor has a 43% lower off current than the conventional asymmetric doping structure. Here, we show the range of the effective buried insulator parameter according to the depth of the buried gate, and we effectively show the range of improvement for the off current.