A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode
NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional
CMOS FA with 0.35 μm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor
(FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.
Simultaneous arrayed formation of single-electron transistors using electromigration in series-connected nanogaps
