scholarly journals Energy efficient high-performance approximate adders for imprecision-tolerant signal processing applications

2021 ◽  
Vol 2107 (1) ◽  
pp. 012065
Author(s):  
K Komathy Vanitha ◽  
S Anila
Keyword(s):  
Signal Processing ◽  
Energy Efficient ◽  
High Performance ◽  
Large Scale ◽  
Approximate Computing ◽  
Process Technology ◽  
Trade Off ◽  
Large Scale Integration ◽  
Power Delay Product ◽  
Scale Integration

Abstract The trade-off between Delay and Power consumption has become a major concern as process technology reached less than 10 nm proximity in the modern Very Large-Scale Integration (VLSI) technology. This trade-off can be compensated with accuracy and is vanquished by the development of Approximate Computing (AC). In this paper, six diverse Approximate Adders (AAs) have been proposed based on logic complexity reduction at the transistor level. Simulation results reveal that the Proposed AAs has a significant amount of Power and Delay savings, lesser Power-Delay Product (PDP). The Proposed AAs:PA1, PA3, PA5, PA3 exhibits 12.85 %, 41.59%, 72.05 %, 1.91% lesser power than the Existing AAs EAA1, EAA5, EAA6, EAA9 respectively. The Proposed AAs: PA2, PA3 incorporates 37.5 %, 54.5%, of lesser number of transistors compared to Existing AAs: EAA5, EAA9 whereas PA4, PA5 incorporates 40 % of reduction in the number of transistors compared to Existing AAs: EAA6, EAA8. These results are promising for high performance and energy efficient systems for error-resilient applications such as multimedia and signal processing where a slightly degraded output quality is acceptable, which could lead to significant power reduction.

scholarly journals Chip on a fiber toward the e-textile computing platform

2020 ◽  
Author(s):  
Sunbin Hwang ◽  
Minji Kang ◽  
Aram Lee ◽  
Sukang Bae ◽  
Seoung-Ki Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Electronic Device ◽  
Electronic Textiles ◽  
Electronic Components ◽  
Computing Platform ◽  
Large Scale Integration ◽  
Circuit Components ◽  
Scale Integration ◽  
Electronic Textile

Abstract Electronic textiles have been considered one of the desired device platforms due to their dimensional compatibility with fabrics by weaving them with yarn. However, the existing electronic textile platforms are generally composed of only one type of electronic component with a single function on a fiber substrate because of processing challenges. A precise connecting process between each electronic fiber is essential to configure the desired electronic circuits or systems. Here we present a chip on a fiber, a new electronic fiber platform, by introducing large scale integration of electronic device or circuit components onto a one-dimensional microfiber substrate. The electronic components such as transistors, inverters, ring oscillators, and thermocouples were integrated together onto the outer surface of a fiber substrate with precise semiconductor and electrode patterns. Our results show that the electronic components can be integrated on a single fiber with reliable operation. We evaluate the electronic properties of the chip on a fiber as a multifunctional electronic textile platform by testing their switching and data processing, as well as sensing or transducing units for detecting optical/thermal signals. The demonstration of the chip on a fiber suggests significant proof of concepts for realization of high performance with wearable electronic textile systems.

Energy-Aware Switch Design

2013 ◽  
pp. 341-360 ◽  
Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Single Chip ◽  
Energy Aware ◽  
It Industry ◽  
Gigabit Ethernet ◽  
Switch Architecture ◽  
Large Scale Integration ◽  
Scale Integration

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.

scholarly journals Application Analysis of Digital Signal Processor DSP in Logging Instrument

2019 ◽  
Vol 3 (2) ◽  
Author(s):  
Jie Lian
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Digital Signal Processor ◽  
Large Scale ◽  
Digital Signal ◽  
Large Scale Integration ◽  
Scale Integration ◽  
Evolution Of Science ◽  
Development And Evolution ◽  
Signal Processor

In today's world, the development of economy has led to the continuous development and evolution of science and technology. Computer technology and large-scale integration technology have been well developed and applied, followed by the technology of digital signal processing DSP production and application. In the field of logging, the application function of this technology plays a key role. It not only allows the imaging logging technology to be further developed, but also enables fast and accurate processing of downhole signals. Therefore, among many logging tools today, digital signal processing DSPs have been widely used, and their functions have been fully utilized. This paper analyzes the application of signal processor DSP in logging instruments. It is hoped that it can play a reference role in the good application and development of logging instruments.

Does 0.1 Micron = MACH 1?

1995 ◽  
Vol 380 ◽  
Author(s):  
R. Fabian Pease
Keyword(s):  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
Commercial Use ◽  
Optical Projection ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
The Cost ◽  
The Military

ABSTRACTThe drive to increasingly higher density ultra-large-scale-integration (ULSI) (of electronic circuits) is fuelled primarily by cost; on-chip interconnects are far cheaper than the less dense offchip interconnects. At the same time the escalating cost of an IC factory (‘fab’) is making headlines as it goes through $1B and a large part of this escalation is the cost of high performance lithography tools. The lithographic technology to go below 0.1μm will almost certainly be very different from an extension of today's optical projection and the cost of replacing today's technology will be enormous. A second drawback to higher density is the resistance of narrow interconnects. As a result some people have suggested that this situation is analogous to that of airliner speed which increased over a period of thirty years from about 100 mph to close to 600 mph but has not increased in the last 35 years. Still faster speed was technically possible, and hence was pursued by the military, but is uneconomical for most commercial use. Current technology might take us to 0.1μm which will probably be state of the art 10 years hence so technologies for replacing optical lithography e.g. scanned arrays of proximal probes should be researched now. Other challenges include how to achieve useful interconnect networks employing 50 nm features.

scholarly journals Realization of Various Gate level Combinational Circuits using Reversible Fredkin Gate

2020 ◽  
Vol 9 (3) ◽  
pp. 4145-4150
Keyword(s):  
Energy Efficient ◽  
Large Scale ◽  
Logic Gates ◽  
Life Time ◽  
Optimization Methods ◽  
Process Data ◽  
Fredkin Gate ◽  
Large Scale Integration ◽  
Aggregation Of Information ◽  
Scale Integration

This paper presents the digital logic gates which are reconstructed using fredkin gate [1]. The advantage of basic fredkin gate is that we could save the thermal waste which comes out due to computation that causes heat as bits just disappear into loss of energy. Such computation won't need any energy input. These assumptions make the gates sound like an energy efficient solution. However the implementation is done at level of logic gates. This can further be used in sequential circuits to increase the life time of transmitter and receiver circuitry of nodes. It will make the transmission and aggregation of information at node very energy efficient. The drawback of this application is it will cost fare amount of time to process data. These technical hurdles will increase latencies at node level. The protocols infused with energy optimization methods and reversible logic gates offered noticeable improvements in achieving performance and ensuring security of data and graphics. Since the 1980s, with work of Fredkin [1], the reversible circuits have been used in building large scale integration of circuits as elementary units of mobile computing, and recently in wireless networks, drug designing and ultra-fast computing technologies [4].

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