scholarly journals Chip on a fiber toward the e-textile computing platform

2020 ◽  
Author(s):  
Sunbin Hwang ◽  
Minji Kang ◽  
Aram Lee ◽  
Sukang Bae ◽  
Seoung-Ki Lee ◽  
...  
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Electronic Device ◽  
Electronic Textiles ◽  
Electronic Components ◽  
Computing Platform ◽  
Large Scale Integration ◽  
Circuit Components ◽  
Scale Integration ◽  
Electronic Textile

Abstract Electronic textiles have been considered one of the desired device platforms due to their dimensional compatibility with fabrics by weaving them with yarn. However, the existing electronic textile platforms are generally composed of only one type of electronic component with a single function on a fiber substrate because of processing challenges. A precise connecting process between each electronic fiber is essential to configure the desired electronic circuits or systems. Here we present a chip on a fiber, a new electronic fiber platform, by introducing large scale integration of electronic device or circuit components onto a one-dimensional microfiber substrate. The electronic components such as transistors, inverters, ring oscillators, and thermocouples were integrated together onto the outer surface of a fiber substrate with precise semiconductor and electrode patterns. Our results show that the electronic components can be integrated on a single fiber with reliable operation. We evaluate the electronic properties of the chip on a fiber as a multifunctional electronic textile platform by testing their switching and data processing, as well as sensing or transducing units for detecting optical/thermal signals. The demonstration of the chip on a fiber suggests significant proof of concepts for realization of high performance with wearable electronic textile systems.

Energy-Aware Switch Design

2013 ◽  
pp. 341-360 ◽  
Author(s):  
Yukihiro Nakagawa ◽  
Takeshi Shimizu ◽  
Takeshi Horie ◽  
Yoichi Koyanagi ◽  
Osamu Shiraki ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Large Scale ◽  
Single Chip ◽  
Energy Aware ◽  
It Industry ◽  
Gigabit Ethernet ◽  
Switch Architecture ◽  
Large Scale Integration ◽  
Scale Integration

The use of virtualization technology has been increasing in the IT industry to consolidate servers and reduce power consumption significantly. Virtualized commodity servers are scaled out in the data center and increase the demand for bandwidth between servers. Therefore, a high performance switch is required. The shared-memory switch is the best performance/cost switch architecture, but it is challenging to satisfy the requirements on the memory bandwidth in a high speed network. In addition, it is challenging to handle variable-length frames in Ethernet. This chapter describes the main challenges in Ethernet switch designs and then energy-aware switch designs, including switch architecture and high speed IO interface. As implementation examples, this chapter also describes a single-chip switch Large Scale Integration (LSI) embedded with high-speed IO interfaces and 10-Gigabit Ethernet (10GbE) switch blade equipped with the switch LSI. The switch blade delivers 100% more performance per watt than other 10GbE switch blades in the industry.

Does 0.1 Micron = MACH 1?

1995 ◽  
Vol 380 ◽  
Author(s):  
R. Fabian Pease
Keyword(s):  
High Performance ◽  
Large Scale ◽  
State Of The Art ◽  
Commercial Use ◽  
Optical Projection ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
The Cost ◽  
The Military

ABSTRACTThe drive to increasingly higher density ultra-large-scale-integration (ULSI) (of electronic circuits) is fuelled primarily by cost; on-chip interconnects are far cheaper than the less dense offchip interconnects. At the same time the escalating cost of an IC factory (‘fab’) is making headlines as it goes through $1B and a large part of this escalation is the cost of high performance lithography tools. The lithographic technology to go below 0.1μm will almost certainly be very different from an extension of today's optical projection and the cost of replacing today's technology will be enormous. A second drawback to higher density is the resistance of narrow interconnects. As a result some people have suggested that this situation is analogous to that of airliner speed which increased over a period of thirty years from about 100 mph to close to 600 mph but has not increased in the last 35 years. Still faster speed was technically possible, and hence was pursued by the military, but is uneconomical for most commercial use. Current technology might take us to 0.1μm which will probably be state of the art 10 years hence so technologies for replacing optical lithography e.g. scanned arrays of proximal probes should be researched now. Other challenges include how to achieve useful interconnect networks employing 50 nm features.

scholarly journals Energy efficient high-performance approximate adders for imprecision-tolerant signal processing applications

2021 ◽  
Vol 2107 (1) ◽  
pp. 012065
Author(s):  
K Komathy Vanitha ◽  
S Anila
Keyword(s):  
Signal Processing ◽  
Energy Efficient ◽  
High Performance ◽  
Large Scale ◽  
Approximate Computing ◽  
Process Technology ◽  
Trade Off ◽  
Large Scale Integration ◽  
Power Delay Product ◽  
Scale Integration

Abstract The trade-off between Delay and Power consumption has become a major concern as process technology reached less than 10 nm proximity in the modern Very Large-Scale Integration (VLSI) technology. This trade-off can be compensated with accuracy and is vanquished by the development of Approximate Computing (AC). In this paper, six diverse Approximate Adders (AAs) have been proposed based on logic complexity reduction at the transistor level. Simulation results reveal that the Proposed AAs has a significant amount of Power and Delay savings, lesser Power-Delay Product (PDP). The Proposed AAs:PA1, PA3, PA5, PA3 exhibits 12.85 %, 41.59%, 72.05 %, 1.91% lesser power than the Existing AAs EAA1, EAA5, EAA6, EAA9 respectively. The Proposed AAs: PA2, PA3 incorporates 37.5 %, 54.5%, of lesser number of transistors compared to Existing AAs: EAA5, EAA9 whereas PA4, PA5 incorporates 40 % of reduction in the number of transistors compared to Existing AAs: EAA6, EAA8. These results are promising for high performance and energy efficient systems for error-resilient applications such as multimedia and signal processing where a slightly degraded output quality is acceptable, which could lead to significant power reduction.

scholarly journals Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020 ◽  
Vol 12 (4) ◽  
pp. 64 ◽  
Author(s):  
Qaiser Ijaz ◽  
El-Bay Bourennane ◽  
Ali Kashif Bashir ◽  
Hira Asghar
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
Open Problems ◽  
Communication Architecture ◽  
Field Programmable ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Standard Terms

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

scholarly journals A Survey on Reconfigurable System-on-Chips

2018 ◽  
Author(s):  
Hung Kiem Nguyen ◽  
Tu Xuan Tran
Keyword(s):  
High Performance ◽  
Large Scale ◽  
Reconfigurable System ◽  
Large Scale Integration ◽  
Reconfigurable Processing ◽  
Key Issues ◽  
Is Integration ◽  
On Chip ◽  
Scale Integration ◽  
Multi Mode

The requirements for high performance and low power consumption are becoming more and more inevitable when designing modern embedded systems, especially for the next generation multi-mode multimedia or communication standards. Ultra large-scale integration reconfigurable System-on-Chips (SoCs) have been proposed to achieve not only better performance and lower energy consumption but also higher flexibility and versatility in comparison with the conventional architectures. The unique characteristic of such systems is integration of many types of heterogeneous reconfigurable processing fabrics based on a Network-on-Chip. This paper analyzes and emphasizes the key research trends of the reconfigurable System-on-Chips (SoCs). Firstly, the emerging hardware architecture of SoCs is highlighted. Afterwards, the key issues of designing the reconfigurable SoCs are discussed, with the focus on the challenges when designing reconfigurable hardware fabrics and reconfigurable Network-on-Chips. Finally, some state-of-the-art reconfigurable SoCs are briefly discussed.

Large-Scale Integration of Semiconductor Nanowires for High-Performance Flexible Electronics

ACS Nano ◽  
2012 ◽  
Vol 6 (3) ◽  
pp. 1888-1900 ◽  
Author(s):  
Xi Liu ◽  
Yun-Ze Long ◽  
Lei Liao ◽  
Xiangfeng Duan ◽  
Zhiyong Fan
Keyword(s):  
Flexible Electronics ◽  
High Performance ◽  
Large Scale ◽  
Semiconductor Nanowires ◽  
Large Scale Integration ◽  
Scale Integration

The large-scale integration of high-performance silicon nanowire field effect transistors

2009 ◽  
Vol 20 (41) ◽  
pp. 415202 ◽  
Author(s):  
Qiliang Li ◽  
Xiaoxiao Zhu ◽  
Yang Yang ◽  
Dimitris E Ioannou ◽  
Hao D Xiong ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Large Scale ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Large Scale Integration ◽  
Scale Integration
Sign in / Sign up

Export Citation Format

Share Document