LDLA14: a 14 Gbps optical transceiver ASIC in 55 nm for NICA multi purpose detector project

2022 ◽  
Vol 17 (01) ◽  
pp. C01027
Author(s):  
Q. Chen ◽  
D. Guo ◽  
C. Zhao ◽  
R. Arteche ◽  
C. Ceballos ◽  
...  

Abstract This paper presents the design and test results of a 14 Gbps optical transceiver ASIC (LDLA14) fabricated in a 55 nm CMOS technology for NICA Multi Purpose Detector (MPD) project. The LDLA14 is a single-channel bidirectional (1Tx + 1Rx) optical transceiver ASIC, including a Laser Driver (LD) module and a Limiting Amplifier (LA) module. It would drive the Vertical Cavity Surface Emitting Laser (VCSEL) of Transmitter Optical Sub-Assembly (TOSA) and receive signals from Photo Diode (PD) of Receiver Optical Sub-Assembly (ROSA), respectively. In the LDLA14, a novel structure of capacitive coupling pre-emphasis is proposed in the output driver of LD to obtain peaking effect without sacrifice the modulation current swing. A shared inductor technology and a Continuous Time Linear Equalizer (CTLE) pre-emphasis structure are added in the output buffer of LA to improve the quality of the output eye diagram. The dimension of LDLA14 is 1.5 mm × 1.3 mm, and the power consumption is 178 mW. The Peak-to-Peak Jitter (PPJ) and Root-Mean-Square Jitter (RMSJ) of the 14 Gbps optical eye diagram of LD in the Tx direction are 22.5 ps and 3.5 ps, respectively. The PPJ and RMSJ of the 14 Gbps electrical eye diagram of LA in the Rx direction are 23.1 ps and 4.7 ps, respectively. The BER tests have been conducted in Tx, Rx directions and the Tx-Rx loop condition, and the BER less than 10−12 is achieved in all tests.

2013 ◽  
Vol 760-762 ◽  
pp. 147-151
Author(s):  
Bing Liang Yu ◽  
Ji Chen ◽  
Wen Yuan Li

A monolithically integrated 10Gbps Vertical Cavity Surface Emitting Laser (VCSEL) current driver is implemented in SMIC 0.18μm RF CMOS technology. High current driving capability as well as agile switching speed is achieved by shunt peaking technique and cascade structure. Test result shows that the driver can drive the common anode VCSEL well working at 10Gbps, and delivers 9.7mA modulation current. With single 1.8V power supply, the core power consumption is 22.5mW and the die size is 800μm×500μm.


2012 ◽  
Vol 588-589 ◽  
pp. 868-871 ◽  
Author(s):  
Jin Fei Wang ◽  
Ying Mei Chen ◽  
Ling Tian ◽  
Li Zhang

A design of 10 Gbps Vertical Cavity Surface Emitting Laser (VCSEL) driver using 0.18µm CMOS technology is presented in this paper. The core unit of the driver consists of pre-amplify stage and output stage circuit. Technique of three stages differential amplifier with low impedance load and active feedback are employed in pre-amplify stage, and technique of C3A is adopted in output stage to get low power consume and high speed. The simulation results show that the circuit can work at the speed rate of 10 Gbps and maximum of 13 Gbps with a 1.8V power supply. The output modulation current is up to 12.5mA and the power dissipation is 77mW. The chip size is 0.45mm  0.47mm.


2003 ◽  
Vol 76 (5) ◽  
pp. 603-608 ◽  
Author(s):  
G. Totschnig ◽  
M. Lackner ◽  
R. Shau ◽  
M. Ortsiefer ◽  
J. Rosskopf ◽  
...  

2006 ◽  
Vol 88 (12) ◽  
pp. 121122
Author(s):  
Florencio D. Recoleto ◽  
Jennette N. Mateo ◽  
Mariel Grace S. Dimamay ◽  
Armando S. Somintac ◽  
Elmer S. Estacio ◽  
...  

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