Impact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective

ABSTRACTNitridation of GeO2 interfacial layer (IL) was done using continuous wave (CW) and pulsed wave (PW) decoupled plasma nitridation (DPN) processes. Langmuir probe analysis of the N2 plasma demonstrates that at the same effective power and pressure, PW plasma has similar electron density (Ne) with lower electron temperature (kTe) and plasma potential (Vp) as compared to CW plasma. This results in softer plasma conditions using a PW process leading to lower plasma-related damage in the IL, but without reducing the overall nitrogen concentration. The plasma parameters were further correlated to mobility (μ) and interface trap density (Dit) extracted from fabricated Ge n-MOSFETs. As expected from the plasma analysis, at the same effective power and pressure, the PW DPN process shows 1.2X higher electron mobility as compared to a CW process. This improvement can enable GeON as an IL for future Ge CMOS gate stack technology.

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High quality interfacial layer formation for Si0.75Ge0.25 (100) high-k metal gate stack

Microelectronic Engineering ◽

10.1016/j.mee.2020.111219 ◽

2020 ◽

Vol 223 ◽

pp. 111219 ◽

Cited By ~ 1

Author(s):

S. Siddiqui ◽

R. Galatage ◽

W. Zhao ◽

G. Raja Muthinti ◽

J. Fronheiser ◽

...

Keyword(s):

Interfacial Layer ◽

Layer Formation ◽

Metal Gate ◽

Gate Stack ◽

High Quality ◽

High K

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PBTI response to interfacial layer thickness variation in Hf-based HKMG nFETs

2010 IEEE International Reliability Physics Symposium ◽

10.1109/irps.2010.5488679 ◽

2010 ◽

Cited By ~ 13

Author(s):

D.P. Ioannou ◽

E. Cartier ◽

Y. Wang ◽

S. Mittl

Keyword(s):

Layer Thickness ◽

Interfacial Layer ◽

Thickness Variation

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Modified Porod's law estimate of the transition-layer thickness between two phases: test of triangular smoothing function

Journal of Applied Crystallography ◽

10.1107/s0021889804013196 ◽

2004 ◽

Vol 37 (4) ◽

pp. 643-651 ◽

Cited By ~ 23

Author(s):

Man-Ho Kim

Keyword(s):

Layer Thickness ◽

Density Profile ◽

Analytical Method ◽

Interfacial Layer ◽

Gaussian Function ◽

Negative Slope ◽

Smoothing Function ◽

Angle Scattering ◽

Dependent Parameter ◽

Two Phases

An analytical method to estimate the thickness of the interface between two phases from small-angle scattering (SAS) data has been developed using Porod's law modified by a triangular smoothing function. The convolution with a `top-hat' function describing a sharp density profile results in a semi-sigmoidal density profile. This analytical method allows an interfacial layer thickness to be estimated from the negative slope of a Porod plot. The interfacial layer thickness (T) obtained from this model is related to similar models, namely a linear (E) and a sigmoidal density profile (σ) model, as follows:T= 21/2E= 2(61/2)σ, where σ is the standard deviation of the Gaussian function and does not represent the boundary thickness itself. The interfacial layer thickness obtained from any convolution method is a model-dependent parameter.

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Reduced Interfacial Layer Thickness and Gate Leakage Current of ALD Grown HfAlO with TaN Gates using Chemical Oxides and Spike-Annealing

10.7567/ssdm.2007.p-1-15 ◽

2007 ◽

Author(s):

Yao-Jen Lee ◽

Bo-An Tsai ◽

Hsin-Yi Peng ◽

Charles Pei-Jer Tzeng ◽

Kuei-Shu Chang-Liao

Keyword(s):

Layer Thickness ◽

Leakage Current ◽

Interfacial Layer ◽

Gate Leakage Current ◽

Gate Leakage ◽

Spike Annealing

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Analysis of Barrier Layer Thickness on Performance of In1–xGaxAs Based Gate Stack Cylindrical Gate Nanowire MOSFET

Journal of Nanoelectronics and Optoelectronics ◽

10.1166/jno.2018.2374 ◽

2018 ◽

Vol 13 (10) ◽

pp. 1473-1477 ◽

Cited By ~ 3

Author(s):

Sanjeev Kumar Sharma ◽

Jeetendra Singh ◽

Balwinder Raj ◽

Mamta Khosla

Keyword(s):

Layer Thickness ◽

Barrier Layer ◽

Significant Variation ◽

Barrier Thickness ◽

Gate Stack ◽

Barrier Layer Thickness ◽

Nanowire Mosfets ◽

Silvaco Atlas ◽

Nanowire Mosfet

In this paper, InGaAs/InP heterostructure based Cylindrical Gate Nanowire MOSFETs (CGNWMOSFET) is designed and its performance has been analyzed using silvaco ATLAS TCAD tool. The influence of the barrier thickness is investigated for perusal performance of an InGaAs/InP heterostructure CGNWMOSFET. The performance compared for various parameters on current, off current, Cut off Frequency (fT), Transconductance (gm), Gate to Source capacitance (Cgs), and Gate to Drain capacitance (Cgd). Results show significant variation in the performance of InGaAs/InP heterostructure CGNWMOSFET by varying the barrier thickness.

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