High Speed Vlsi Architectures Of Fir Filters For Image Applications – A Review

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Download Full-text

High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

International Journal of Reconfigurable Computing ◽

10.1155/2015/518272 ◽

2015 ◽

Vol 2015 ◽

pp. 1-16 ◽

Cited By ~ 4

Author(s):

Burhan Khurshid ◽

Roohie Naaz Mir

Keyword(s):

Power Dissipation ◽

High Speed ◽

High Efficiency ◽

Critical Path ◽

Fir Filters ◽

Path Delay ◽

Look Up Table ◽

Improved Performance ◽

Ip Cores ◽

Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

Download Full-text

Constant-coefficient FIR filters based on residue number system arithmetic

Serbian Journal of Electrical Engineering ◽

10.2298/sjee1203325s ◽

2012 ◽

Vol 9 (3) ◽

pp. 325-342 ◽

Cited By ~ 1

Author(s):

Negovan Stamenkovic ◽

Vladica Stojanovic

Keyword(s):

Power Dissipation ◽

High Speed ◽

Finite Impulse Response ◽

Number System ◽

Residue Number System ◽

Fir Filter ◽

Fir Filters ◽

Residue Number ◽

Low Power Dissipation ◽

Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

Download Full-text