scholarly journals Design of basic logic gates using optical threshold logic

2021 ◽  
Author(s):  
Mili Sarkar ◽  
Rijuparna Chakraborty ◽  
Gouranga Sundar Taki ◽  
Ajoy Kumar Chakraborty
Keyword(s):  
Logic Gates ◽  
Threshold Logic ◽  
Basic Logic

scholarly journals Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates

2003 ◽  
Vol 26 (2) ◽  
pp. 111-114 ◽  
Author(s):  
Muhammad Taher Abuelma'atti
Keyword(s):  
Power Series ◽  
Low Voltage ◽  
Logic Gates ◽  
Current Mode ◽  
New Technique ◽  
Basic Logic ◽  
Spice Simulation ◽  
Simulation Results ◽  
A New Technique ◽  
Logic Functions

In this letter a new technique is introduced for implementing the basic logic functions using analog current-mode techniques. By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. To illustrate the proposed technique, a circuit for simultaneous realization of the logic functions NOT, OR, NAND and XOR is considered. SPICE simulation results, obtained with 3 V supply, are included

scholarly journals Practical Implementation of Memristor-Based Threshold Logic Gates

2019 ◽  
Vol 66 (8) ◽  
pp. 3041-3051 ◽  
Author(s):  
Georgios Papandroulidakis ◽  
Alexander Serb ◽  
Ali Khiat ◽  
Geoff V. Merrett ◽  
Themis Prodromakis
Keyword(s):  
Logic Gates ◽  
Practical Implementation ◽  
Threshold Logic

The Optimizations of Dual-Threshold Independent-Gate FinFETs and Low-Power Circuit Designs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050114
Author(s):  
Haiyan Ni ◽  
Jianping Hu ◽  
Xuqiang Zhang ◽  
Haotian Zhu
Keyword(s):  
Synthesis Method ◽  
Logic Gates ◽  
Oxide Thickness ◽  
High Threshold ◽  
Basic Logic ◽  
Power Circuit ◽  
Gate Oxide Thickness ◽  
Threshold Device ◽  
Low Threshold ◽  
Independent Gate

In this paper, a method of optimizing dual-threshold independent-gate FinFET devices is discussed, and the optimal circuit design is carried out by using these optimized devices. Dual-threshold independent-gate FinFETs include low threshold devices and high threshold devices. The low threshold device is equivalent to two merging parallel short-gate devices and high threshold device is equivalent to two merging series SG devices. We optimize the device mainly by selecting the appropriate gate work function, gate oxide thickness, silicon body thickness and so on. Our optimization is based on the Berkeley BSIMIMG model and verified by TCAD tool. Based on these optimized devices, we designed the compact basic logic gates and two new compact D-type flip-flops. Additionally, we developed a circuit synthesis method based on Binary Decision Diagram (BDD) and the optimized compact basic logic gates. Hspice simulations show that the circuits using the proposed dual-threshold IG FinFETs have better performance than the circuits directly using the short-gate devices.

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