A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management

2010 ◽  
Vol 45 (1) ◽  
pp. 103-110 ◽  
Author(s):  
Yih Wang ◽  
Uddalak Bhattacharya ◽  
Fatih Hamzaoglu ◽  
Pramod Kolar ◽  
Yong-Gee Ng ◽  
...  
Keyword(s):  
Power Management ◽  
Cmos Technology ◽  
Metal Gate ◽  
High K ◽  
Sram Design

A 3.8 GHz 153 Mb SRAM Design With Dynamic Stability Enhancement and Leakage Reduction in 45 nm High-k Metal Gate CMOS Technology

2009 ◽  
Vol 44 (1) ◽  
pp. 148-154 ◽  
Author(s):  
Fatih Hamzaoglu ◽  
Kevin Zhang ◽  
Yih Wang ◽  
Hong Jo Ahn ◽  
Uddalak Bhattacharya ◽  
...  
Keyword(s):  
Dynamic Stability ◽  
Cmos Technology ◽  
Metal Gate ◽  
Leakage Reduction ◽  
High K ◽  
Sram Design ◽  
Stability Enhancement

High performance FDSOI CMOS technology with metal gate and high-k

2005 ◽  
Author(s):  
B. Doris ◽  
Y.H. Kim ◽  
B.P. Linder ◽  
M. Steen ◽  
V. Narayanan ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Metal Gate ◽  
High K

Large signal microwave performances of high-k metal gate 28 nm CMOS technology

2012 ◽  
Vol 48 (25) ◽  
pp. 1627-1629 ◽  
Author(s):  
R. Ouhachi ◽  
A. Pottrain ◽  
D. Gloria ◽  
C. Gaquière ◽  
D. Ducatteau ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Large Signal ◽  
Metal Gate ◽  
High K ◽  
28 Nm

RF CMOS technology scaling in High-k/metal gate era for RF SoC (system-on-chip) applications

2010 ◽  
Author(s):  
C.-H. Jan ◽  
M. Agostinelli ◽  
H. Deshpande ◽  
M. A. El-Tanani ◽  
W. Hafez ◽  
...  
Keyword(s):  
Cmos Technology ◽  
System On Chip ◽  
Rf Cmos ◽  
Metal Gate ◽  
Technology Scaling ◽  
High K ◽  
On Chip

A novel low resistance gate fill for extreme gate length scaling at 20nm and beyond for gate-last high-k/metal gate CMOS technology

2012 ◽  
Author(s):  
U. Kwon ◽  
K. Wong ◽  
S. A. Krishnan ◽  
L. Econimikos ◽  
X. Zhang ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Gate Length ◽  
Metal Gate ◽  
Low Resistance ◽  
High K ◽  
Length Scaling

Wafer Level Statistical Evaluation of the Proton Radiation Hardness of a High-k Dielectric/Metal Gate 45 nm Bulk CMOS Technology

2013 ◽  
Vol 50 (5) ◽  
pp. 213-222
Author(s):  
C. Claeys ◽  
S. Iacovo ◽  
D. Kobayashi ◽  
A. Mercha ◽  
A. Griffoni ◽  
...  
Keyword(s):  
Statistical Evaluation ◽  
Cmos Technology ◽  
Radiation Hardness ◽  
Proton Radiation ◽  
Wafer Level ◽  
Metal Gate ◽  
High K ◽  
High K Dielectric
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