Electrical investigation of Cu pumping in through-silicon vias for BEOL reliability in 3D integration

2015 ◽  
Author(s):  
Chuan-An Cheng ◽  
Ryuichi Sugie ◽  
Tomoyuki Uchida ◽  
Kou-Hua Chen ◽  
Chi-Tsung Chiu ◽  
...  
Keyword(s):  
3D Integration ◽  
Through Silicon Vias ◽  
Electrical Investigation ◽  
Silicon Vias

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Characterization and Failure Analysis of Wafer Bonded Devices and Unfilled Through-Silicon-Vias (TSVs)

2008 ◽  
Author(s):  
C. Cassidy ◽  
J. Kraft ◽  
G. Koppitsch ◽  
E. Brandlhofer ◽  
M. Steiner ◽  
...  
Keyword(s):  
Sample Preparation ◽  
Failure Analysis ◽  
Semiconductor Devices ◽  
3D Integration ◽  
Through Silicon Vias ◽  
Silicon Vias

Abstract This paper is concerned with characterization and failure analysis challenges posed by 3D integration of semiconductor devices, with a particular focus on wafer bonded components and Through Silicon Vias (TSV). Requirements for sample preparation are discussed, along with advantages and limitations exhibited by various different techniques. Analysis examples with real devices are presented, along with successful sample preparation solutions enabled by a precision polishing toolset.

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

2012 ◽  
Vol 9 (1) ◽  
pp. 31-36 ◽  
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
Cross Sections ◽  
3D Integration ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

A Prospective Low-k Insulator for Via-Last through-Silicon-Vias (TSVs) in 3D Integration

2016 ◽  
Author(s):  
Tung Thanh Bui ◽  
Xiaojin Cheng ◽  
Naoya Watanabe ◽  
Fumiki Kato ◽  
Katsuya Kikuchi ◽  
...  
Keyword(s):  
3D Integration ◽  
Through Silicon Vias ◽  
Silicon Vias ◽  
Low K

Experimental characterization of coaxial through silicon vias for 3D integration

2015 ◽  
Vol 46 (5) ◽  
pp. 377-382 ◽  
Author(s):  
Stephen Adamshick ◽  
Douglas Coolbaugh ◽  
Michael Liehr
Keyword(s):  
Experimental Characterization ◽  
3D Integration ◽  
Through Silicon Vias ◽  
Silicon Vias

A New Prewetting Process of Through Silicon Vias (TSV) Electroplating for 3D Integration

2019 ◽  
Vol 28 (3) ◽  
pp. 447-452 ◽  
Author(s):  
Cao Li ◽  
Jun Nie ◽  
Jinglong Zou ◽  
Sheng Liu ◽  
Huai Zheng ◽  
...  
Keyword(s):  
3D Integration ◽  
Through Silicon Vias ◽  
Silicon Vias
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