Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

2011 ◽  
Vol 2011 (1) ◽  
pp. 000001-000007
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Cross Sections ◽  
3D Integration ◽  
Leakage Currents ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

2012 ◽  
Vol 9 (1) ◽  
pp. 31-36 ◽  
Author(s):  
Chien-Ying Wu ◽  
Shang-Chun Chen ◽  
Pei-Jer Tzeng ◽  
John H. Lau ◽  
Yi-Feng Hsu ◽  
...  
Keyword(s):  
Leakage Current ◽  
Cross Sections ◽  
3D Integration ◽  
3D Ic ◽  
Through Silicon Vias ◽  
Enabling Technologies ◽  
Key Enabling Technologies ◽  
Silicon Vias ◽  
Seed Layers

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

Reliable Design of Electroplated Copper Through Silicon Vias

2010 ◽  
Author(s):  
Xi Liu ◽  
Qiao Chen ◽  
Venkatesh Sundaram ◽  
Sriram Muthukumar ◽  
Rao R. Tummala ◽  
...  
Keyword(s):  
System Integration ◽  
Coefficient Of Thermal Expansion ◽  
Three Dimensional ◽  
Interfacial Stress ◽  
Through Silicon Vias ◽  
Fabrication Defects ◽  
Reliable Design ◽  
Electroplated Copper ◽  
Key Enabling Technologies ◽  
Silicon Vias

Through-silicon vias (TSVs), being one of the key enabling technologies for 3D system integration, are being used in various 3D vertically stacked devices. As TSVs are relatively new, there is not enough information in available literature on the thermo-mechanical reliability of TSVs. Due to the high coefficient of thermal expansion (CTE) mismatch between Si and the Cu vias, “Cu pumping” will occur at high temperature and “Cu sinking” will occur at low temperature, which may induce large stress in SiO2, interfacial stress at Cu/SiO2 interface and plastic deformation in Cu core. The thermal-mechanical stress can potentially cause interfacial debonding, cohesive cracking in dielectric layers or Cu core, causing some reliability issues. Thus, in this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in the TSV structures. A comparative analysis of different via designs, such as circular, square, and annular vias has been performed. In addition, defects due to fabrication such as voids in the Cu core during electroplating and Cu pad undercutting due to over-etching are considered in the models, and it is seen that these fabrication defects are detrimental to TSV reliability.

RF Modeling of Through Silicon Vias (TSVs) in 3D IC

2010 ◽  
Author(s):  
C. W. Luo ◽  
Y. C. Wu ◽  
J. Y. Wang ◽  
S. S. H. Hsu
Keyword(s):  
3D Ic ◽  
Through Silicon Vias ◽  
Silicon Vias
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