Automated Measurement and Analysis of Sidewall Roughness (SWR) Using 3D-AFM

As the semiconductor device architecture develops, from planar field-effect transistor (FET) to FinFET and toward gate all around (GAA), it is more needed to measure 3D structure sidewall precisely. Here, we present a 3D-atomic force microscopy (3D-AFM) by Park Systems Corp., a powerful 3D metrology tool to measure SWR of vertical and undercut structures. First, we measured 3 different dies repeatedly to calculate reproducibility in die level. Reproducible results were derived with relative standard deviation under 2%. Second, we measured 13 different dies, including the center and edge of the wafer, to analyze SWR distribution in wafer level and reliable results were measured. And all analysis was performed using a novel algorithm including auto flattening, sidewall detection, and SWR calculation. In addition, SWR automatic analysis software was implemented to reduce analysis time and to provide standard analysis. The result suggests that our 3D-AFM based on tilted Z scanner enabled an advanced methodology for automated 3D measurement and analysis.

SOFTWARE COMPLEX FOR PHOTOLITHOGRAPHY OPTIMIZATION FOR MINIMIZATION OF SIDEWALL ROUGHNESS EFFECTS IN NANOSTRUCTURES. GROUNDS AND PROBLEM STATEMENT

Sidewall roughness is an effect occurred during micro- and nanoelectronics’ structure formation using photolithography. In this work we describe the basic model of roughness emergence on nanostructures’ sidewalls, and determine the approach of photolithography parameters optimization in order to minimize the roughness. the standard route of test structures formation is considered. We develop a software complex based on this approach.

Computer simulation study about the dependence of amorphous silicon photonic waveguides efficiency on the material quality

Amorphous silicon PECVD photonic integrated devices are promising candidates for low cost sensing applications. This manuscript reports a simulation analysis about the impact on the overall efficiency caused by the lithography imperfections in the deposition process. The tolerance to the fabrication defects of a photonic sensor based on surface plasmonic resonance is analysed. The simulations are performed with FDTD and BPM algorithms. The device is a plasmonic interferometer composed by an a-Si:H waveguide covered by a thin gold layer. The sensing analysis is performed by equally splitting the input light into two arms, allowing the sensor to be calibrated by its reference arm. Two different 1 × 2 power splitter configurations are presented: a directional coupler and a multimode interference splitter. The waveguide sidewall roughness is considered as the major negative effect caused by deposition imperfections. The simulation results show that plasmonic effects can be excited in the interferometric waveguide structure, allowing a sensing device with enough sensitivity to support the functioning of a bio sensor for high throughput screening. In addition, the good tolerance to the waveguide wall roughness, points out the PECVD deposition technique as reliable method for the overall sensor system to be produced in a low-cost system. The large area deposition of photonics structures, allowed by the PECVD method, can be explored to design a multiplexed system for analysis of multiple biomarkers to further increase the tolerance to fabrication defects.

Optimization of Single-Step UV Exposure for Fabrication of Integrated Optical Device by Imprinting

In this paper, a single ultra-violet exposure for multi-height structure was used to fabricate an optical-fiberintegrated planar lightwave circuit (PLC) splitter using a thermal imprinting technique. The 1 × 8 tapered multimode PLC splitter was designed with a trench at a depth of 50 μm and a variable width ranging from 50 μm to 690 μm for the insertion of waveguide and fiber structures measuring 125 μm × 87.5 μm in order to minimize insertion loss. Photolithography with a Cr layer and bottom anti-reflection coating (BARC) was utilized to fabricate a multi-height photoresist structure, and the effect of the thick Cr layer and BARC on the geometry was investigated. Scanning electron microscopy of the fabricated structures showed that a Cr thickness of 50 nm and BARC provided the ideal geometry with a minimal undercut and sidewall roughness. Based on the characterization of the imprinted splitter, the average value and uniformity of optical loss between the channels were 10 dB and less than 0.42 dB, respectively.

Investigation for Sidewall Roughness Caused Optical Scattering Loss of Silicon-on-Insulator Waveguides with Confocal Laser Scanning Microscopy

Sidewall roughness-caused optical loss of waveguides is one of the critical limitations to the proliferation of the silicon photonic integrated circuits in fiber-optic communications and optical interconnects in computers, so it is imperative to investigate the distribution characteristics of sidewall roughness and its impact upon the optical losses. In this article, we investigated the distribution properties of waveguide sidewall roughness (SWR) with the analysis for the three-dimensional (3-D) SWR of dielectric waveguides, and, then the accurate SWR measurements for silicon-on-insulator (SOI) waveguide were carried out with confocal laser scanning microscopy (CLSM). Further, we composed a theoretical/experimental combinative model of the SWR-caused optical propagation loss. Consequently, with the systematic simulations for the characteristics of optical propagation loss of SOI waveguides, the two critical points were found: (i) the sidewall roughness-caused optical loss was synchronously dependent on the correlation length and the waveguide width in addition to the SWR and (ii) the theoretical upper limit of the correlation length was the bottleneck to compressing the roughness-induced optical loss. The simulation results for the optical loss characteristics, including the differences between the TE and TM modes, were in accord with the experimental data published in the literature. The above research outcomes are very sustainable to the selection of coatings before/after the SOI waveguide fabrication.