Performance Assessment of UTB-SOI MOS Transistor with Negative Capacitance Gate-stack

2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC) ◽

10.1109/aespc44649.2018.9033231 ◽

2018 ◽

Author(s):

Elina Priyadarshini ◽

Subir Kumar Maity

Keyword(s):

Performance Assessment ◽

Negative Capacitance ◽

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Sub-Threshold Performance Assessment of Ultra-Thin Body InGaAs-on Insulator Negative Capacitance MOS Transistor

Silicon ◽

10.1007/s12633-019-00364-6 ◽

2020 ◽

Vol 12 (11) ◽

pp. 2681-2688

Author(s):

Subir Kumar Maity

Keyword(s):

Performance Assessment ◽

Thin Body ◽

Negative Capacitance ◽

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Harnessing Maximum Negative Capacitance Signature Voltage Window in P(VDF-TrFE) Gate Stack

2021 IEEE International Symposium on Circuits and Systems (ISCAS) ◽

10.1109/iscas51556.2021.9401100 ◽

2021 ◽

Author(s):

Khoirom Johnson Singh ◽

Anand Bulusu ◽

Sudeb Dasgupta

Keyword(s):

Negative Capacitance ◽

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Static Performance Assessment of Junctionless Accumulation Mode Gate Stack Gate All Around (JAM-GS-GAA) FinFET Under Severe Temperature

10.1109/icsc53193.2021.9673255 ◽

2021 ◽

Author(s):

Bhavya Kumar ◽

Megha Sharma ◽

Rishu Chaujar

Keyword(s):

Performance Assessment ◽

Accumulation Mode ◽

Static Performance

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Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack

IEEE Electron Device Letters ◽

10.1109/led.2019.2951705 ◽

2020 ◽

Vol 41 (1) ◽

pp. 179-182 ◽

Author(s):

Daewoong Kwon ◽

Suraj Cheema ◽

Yen-Kai Lin ◽

Yu-Hung Liao ◽

Korok Chatterjee ◽

...

Keyword(s):

Oxide Thickness ◽

Negative Capacitance ◽

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Double Gate Graded Channel Negative Capacitance FET (DGGCNCFET): Performance Assessment for Low Power Digital/Analog Applications

2018 International Conference on Computing, Power and Communication Technologies (GUCON) ◽

10.1109/gucon.2018.8674968 ◽

2018 ◽

Author(s):

Hema Mehta ◽

Harsupreet Kaur

Keyword(s):

Low Power ◽

Performance Assessment ◽

Negative Capacitance ◽

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Impact of total and partial dipole switching on the switching slope of gate-last negative capacitance FETs with ferroelectric hafnium zirconium oxide gate stack

2017 Symposium on VLSI Technology ◽

10.23919/vlsit.2017.7998160 ◽

2017 ◽

Author(s):

P. Sharma ◽

K. Tapily ◽

A. K. Saha ◽

J. Zhang ◽

A. Shaughnessy ◽

...

Keyword(s):

Zirconium Oxide ◽

Negative Capacitance ◽

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Effects of Gate Stack Composition and Thickness in 2-D Negative Capacitance FETs

IEEE Journal of the Electron Devices Society ◽

10.1109/jeds.2019.2922441 ◽

2019 ◽

Vol 7 ◽

pp. 645-649

Author(s):

Yuh-Chen Lin ◽

Felicia McGuire ◽

Steven Noyce ◽

Nicholas Williams ◽

Zhihui Cheng ◽

...

Keyword(s):

Negative Capacitance ◽

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On gate stack scalability of Double-Gate Negative-Capacitance FET with ferroelectric HfO2 for energy-efficient sub-0.2V operation

2016 IEEE Silicon Nanoelectronics Workshop (SNW) ◽

10.1109/snw.2016.7578039 ◽

2016 ◽

Author(s):

Kyungmin Jang ◽

Takuya Saraya ◽

Masaharu Kobayashi ◽

Toshiro Hiramoto

Keyword(s):

Energy Efficient ◽

Negative Capacitance ◽

Double Gate ◽

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Experimental Demonstration of Negative Capacitance epi-Ge/Si FETs with Ferroelectric Hf-based Oxide Gate Stack for Swing Sub-60mV/dec and Hysteresis-Free

10.7567/ssdm.2016.a-2-01 ◽

2016 ◽

Author(s):

M.H. Lee ◽

P.G. Chen ◽

C. Liu ◽

K.T. Chen ◽

M.J. Xie ◽

...

Keyword(s):

Negative Capacitance ◽

Experimental Demonstration ◽

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Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack

Japanese Journal of Applied Physics ◽

10.7567/jjap.55.04eb08 ◽

2016 ◽

Vol 55 (4S) ◽

pp. 04EB08 ◽

Author(s):

Chien Liu ◽

Ping-Guang Chen ◽

Meng-Jie Xie ◽

Shao-Nong Liu ◽

Jun-Wei Lee ◽

...

Keyword(s):

Field Effect ◽

Field Effect Transistor ◽

Negative Capacitance ◽

Double Gate ◽

Simulation Based ◽

Effect Transistor ◽

Tunnel Field Effect Transistor

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