<div>In this work, we report that the AFE/FE gate-stack can be utilized to engineer the S-curve for boosting the I<sub>ON</sub> of NC-FinFET. By using a short-channel BSIM-CMG compatible AFE/FE stack NC-FinFET model, the capacitance matching and ON-state performance for AFE/FE stack NC-FinFETs are investigated. Our study indicates that, the AFE/FE gate-stack can be used to improve the capacitance matching in strong inversion at higher gate-bias. Therefore, impressively higher ON-state current (compared to single-layer) can be achieved. In reality, source-drain series resistance will make such high IDS impractical. The more likely strategy is to use lower V<sub>DD</sub> to achieve much lower power consumption (and reduced vertical fields). While the transient NC effect also needs to be carefully investigated, this study suggests significant long term benefits to V<sub>DD</sub> scaling if materials with certain AFE and FE properties are developed and introduced in IC manufacturing in the future.</div>
Near Threshold Capacitance Matching in a Negative Capacitance FET With 1 nm Effective Oxide Thickness Gate Stack