A low gain error two-stage dB-linear variable gain amplifier in 0.35μm CMOS process

2017 ◽  
Author(s):  
Yongsheng Wang ◽  
Xinzhi Li ◽  
Zhixin Zhang ◽  
Fengchang Lai
Keyword(s):  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Two Stage ◽  
Variable Gain ◽  
Gain Error

A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

2019 ◽  
Vol 7 ◽  
Author(s):  
Jorge Pérez Bailón ◽  
Jaime Ramírez-Angulo ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Power Consumption ◽  
Active Area ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Current Steering ◽  
Impedance Sensing ◽  
Variable Gain ◽  
Fully Differential ◽  
Sensing Applications ◽  
Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

An Energy-Efficient Receiver for Human Body Communication

2012 ◽  
Vol 195-196 ◽  
pp. 84-89
Author(s):  
Da Hui Zhang ◽  
Ze Dong Nie ◽  
Feng Guan ◽  
Lei Wang
Keyword(s):  
Low Power ◽  
Human Body ◽  
Data Transmission ◽  
Energy Efficient ◽  
Low Noise ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Variable Gain ◽  
Active Balun ◽  
Noise Amplifier

A low-power, wideband signaling receiver for data transmission through a human body was presented in this paper. The receiver utilized a novel implementation of energy-efficient wideband impulse communication that uses the human body as the transmission medium, provides low power consumption, high reception sensitivity. The receiver consists of a low-noise amplifier, active balun, variable gain amplifier (VGA) Gm-C filter, comparator, and FSK demodulator. It was designed with 0.18um CMOS process in an active area of 1.54mm0.414mm. Post-simulation showed that the receiver has a gain range of-2dB~40dB. The receiver consumes 4mW at 1.8V supply and achieves transmission bit energy of 0.8nJ/bit.

scholarly journals Continuous-TimeΣΔADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Fang Tang ◽  
Amine Bermak ◽  
Amira Abbes ◽  
Mohieddine Amor Benammar
Keyword(s):  
Power Consumption ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Clock Frequency ◽  
Pixel Resolution ◽  
Loop Filter ◽  
Sigma Delta ◽  
Variable Gain

This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

scholarly journals A 40 MHz 70 dB Gain Variable Gain Amplifier Design Using the gm/ID Design Method

2009 ◽  
Vol 4 (1) ◽  
pp. 7-12
Author(s):  
Fernando Paixão Cortes ◽  
Sergio Bampi
Keyword(s):  
Design Method ◽  
Gain Control ◽  
Variable Gain Amplifier ◽  
Cmos Process ◽  
Offset Cancellation ◽  
Variable Gain ◽  
Offset Voltage ◽  
Amplifier Design ◽  
Time Offset ◽  
Bond Pads

This paper addresses the design and post-fabrication measurements of a 40 MHz CMOS Variable Gain Amplifier (VGA) with a 0 to 70 dB gain control range, using the gm/ID design methodology. The VGA architecture is based on a differential pair stage with an automatic continuous-time offset cancellation circuitry, providing an input offset voltage tolerance up to 50 mV. The 3-stage VGA was designed and fabricated through MOSIS service in an IBM 0.18 μm CMOS process. The VGA dissipates 2.6 mA from a 1.8 V supply, with 34,840 μm2 circuit area, excluding bond-pads.

A 90 dB 1.32 mW 1.2 V 0.13 mm2 Two-Stage Variable Gain Amplifier in 0.18  m CMOS

2008 ◽  
Vol E91-C (5) ◽  
pp. 806-808
Author(s):  
Q.-H. DUONG ◽  
J.-S. LEE ◽  
S.-H. MIN ◽  
J.-J. KIM ◽  
S.-G. LEE
Keyword(s):  
Variable Gain Amplifier ◽  
Two Stage ◽  
Variable Gain
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