A study of 10-bit 2-MS/s Successive Approximation Register ADC with low power in 180nm technology

2021 ◽  
Author(s):  
Nam Anh Ha ◽  
Trang Hoang
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Successive Approximation Register

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450023
Author(s):  
MOHAMED O. SHAKER ◽  
MAGDY A. BAYOUMI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
Power Supply ◽  
Cmos Technology ◽  
Clock Signal ◽  
Switching Activity ◽  
Successive Approximation Register ◽  
Simulation Results ◽  
Data Switching

A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications. The proposed register consisting of 8 bits has been designed up to the layout level with 1 V power supply in 90 nm CMOS technology and has been simulated using SPECTRE. Simulation results have shown that the proposed register saves up to 75% of power consumption.

A low power 12-bit 1 Msps successive approximation register ADC with an improved switching procedure

2015 ◽  
Vol 36 (8) ◽  
pp. 085007
Author(s):  
Fubin Xin ◽  
Tao Yin ◽  
Qisong Wu ◽  
Yuanlong Yang ◽  
Fei Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Successive Approximation ◽  
Successive Approximation Register
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