Low-Hardware-Cost SNN employing FeFET-based Neurons with Tunable Leaky Effect

Author(s):  
Hongyi Liu ◽  
Xiangao Qi ◽  
Yuqing Lou ◽  
Liang Qi ◽  
Zuo-Wei Yeh ◽  
...  
Keyword(s):  
Author(s):  
N Ravi Kiran ◽  
G Harish ◽  
A Karthik ◽  
Siva Yellampalli
Keyword(s):  

2013 ◽  
Vol 303-306 ◽  
pp. 578-581
Author(s):  
Kai Tuo Du ◽  
Zhen Ya Zhang ◽  
Hong Mei Cheng ◽  
Qian Sheng Fang

The process of building environmental information perception can be constructed with wireless sensor network (WSN) expediently. A WSN based information acquisition system for building running environment is described in this paper. The CPU of host computer in the system is Loongson2F and wireless nodes in the system are implemented as Telsob nodes. Because the price of wireless node is low, the hardware cost of the desired system is decreased evidently and the security of the desired system is enhanced because the CPU of the host is native. With those features, the application scenario of the desired system is extended widely. To verify the suitability of the using of Collection Tree Protocol (CTP) in construction of the WSN in the desired information acquisition system, the performance of the CTP based WSN deployed in public building space for environment information acquiring are tested and solutions for some key problems in the construction and the maintenance of the CTP based WSN are given in this paper too.


Author(s):  
Donald MacKenzie ◽  
Melissa Parlanti
Keyword(s):  

2000 ◽  
Vol 49 (7) ◽  
pp. 716-726 ◽  
Author(s):  
Chichyang Chen ◽  
Rui-Lin Chen ◽  
Chih-Huan Yang
Keyword(s):  

Author(s):  
M. M. Wong ◽  
M. L. D. Wong

This chapter presents a new area-efficient composite field inverter of the form GF(q1) with q=2n.m suitable for the hardware realization of an elliptic curve (EC) cryptosystem. Considering both the security aspect and the hardware cost required, the authors propose the utilization of the composite field GF(((22)2)41) for EC cryptosystem. For efficient implementation, they have derived a compact inversion circuit over GF(2164)=GF(((22)2)41) to achieve an optimal saving in the hardware cost required. Furthermore, the authors have also developed a composite field digit serial Sunar-Koc multiplier for the multiplication in the extension field. All of the arithmetic operations in the subfield GF(24) are performed in its isomorphic composite field, GF((22)2), leading to a full combinatorial implementation without resorting to the conventional look-up table approach. To summarize the work, the final hardware implementation and the complexity analysis of the inversion is reported towards the end of this chapter.


Author(s):  
Amitabha Chakrabarty ◽  
Martin Collier

Symmetric rearrangeable networks (SRN) (Chakrabarty, Collier, & Mukhopadhyay, 2009) make efficient use of hardware, but they have the disadvantage of momentarily disrupting the existing communications during reconfiguration. Path continuity is a major issue in some application of rearrangeable networks. Using repackable networks (Yanga, Su, & Pin, 2008) is a solution to the path continuity problem in SRN. These networks provide functionality comparable to that of strict sense no blocking networks (SNB) but with minimum increase in the hardware than SRN. This paper proposes an efficient implementation of multistage symmetric repackable networks requiring optimum hardware cost than the method proposed in the literature. Cost optimization is achieved through the use of minimum number of bypass link(s). Investigated method works for networks built with more than three switching stages and shows promise of scalability.


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