Comparison of a new multiple radix fast Fourier number theoretic transform with FFT algorithms in terms of performance and hardware cost

2002 ◽  
Author(s):  
R. Polge ◽  
B. Lawrence
Keyword(s):  
Fourier Number ◽  
Hardware Cost ◽  
Fft Algorithms

Low power and hardware cost STUMPS BIST

2015 ◽  
Author(s):  
N Ravi Kiran ◽  
G Harish ◽  
A Karthik ◽  
Siva Yellampalli
Keyword(s):  
Low Power ◽  
Hardware Cost

Performance Analysis of an Area Efficient and Low Power MOD-R2MDC FFT for MIMO OFDM

2014 ◽  
Vol 573 ◽  
pp. 176-180
Author(s):  
G. Kavitha ◽  
B. Kirthiga ◽  
N. Kirubanandasarathy
Keyword(s):  
Low Power ◽  
Orthogonal Frequency Division Multiplexing ◽  
Ofdm System ◽  
Description Language ◽  
Fft Processor ◽  
Synthesis Tool ◽  
Mimo Ofdm ◽  
Hardware Description ◽  
Fft Algorithms ◽  
Area Efficient

In this paper, an area-efficient low power fast fourier transform (FFT) processor is proposed for multi input multi output-orthogonal frequency division multiplexing (MIMO-OFDM) in wireless communication system. It consists of a modified architecture of radix-2 algorithm which is described as modified radix-2 multipath delay commutation (MOD-R2MDC). The OFDM receiver with modified R2MDC (MOD-R2MDC) FFT was designed by Hardware Description Language (HDL) coding The Xilinx ISE Design Suite 10.1 is used as a synthesis tool for getting the power and area. The Model-Sim 6.3c is used for simulation. Also the existing OFDM system has been tested with these FFT algorithms and their performances were analyzed with respect to occupancy area in FPGA and power consumption. A low-power and area efficient architecture enables the real-time operations of MIMO OFDM system.

PARALLEL FFT ALGORITHMS ON NETWORK-ON-CHIPS

2009 ◽  
Vol 18 (02) ◽  
pp. 255-269 ◽  
Author(s):  
JUN HO BAHN ◽  
JUNG SOOK YANG ◽  
WEN-HSIANG HU ◽  
NADER BAGHERZADEH
Keyword(s):  
Data Communication ◽  
Digital Signal ◽  
Variable Number ◽  
Data Locality ◽  
Communication Traffic ◽  
On Chip ◽  
Fft Algorithms ◽  
Signal Processors ◽  
Parallel Fft ◽  
Parallel Fft Algorithm

This paper presents parallel FFT algorithms with different degree of computation and communication overheads for multiprocessors in a Network-on-Chip (NoC) environment. Of the three parallel FFT algorithms presented in this paper, we propose two parallel FFT algorithms for a 2D NoC that can contain a variable number of processing elements (PEs) and one is a reference parallel FFT algorithm for comparison. A parallel FFT algorithm we propose increases performance by assigning well-balanced computation tasks to PEs. The execution times are reduced because the algorithm uses data locality well to avoid unnecessary data exchanges among PEs and removes the overall idle periods by2 a balanced task scheduling. An enhanced version of this algorithm is suggested in which communication traffic is reduced. In this algorithm, returning transformed data to an original PE after one computation stage before sending them to a next PE for the following stage is removed. Instead, we propose a method that enables to keep regularity of the data communication and computations with twiddle factors. According to the simulation result from our cycle-accurate SystemC NoC model with a parametrizable 2-D mesh architecture, and the analysis of the algorithms in time and complexity, our proposed algorithms are shown to outperform the reference parallel FFT algorithm and FFT implementations on TI Digital Signal Processors (DSPs) that have similar specifications to our simulation environment.

The Design and Implementation of an Information Acquisition System for Building Running Environment Based on Wireless Sensor Network and Loongson2F

2013 ◽  
Vol 303-306 ◽  
pp. 578-581
Author(s):  
Kai Tuo Du ◽  
Zhen Ya Zhang ◽  
Hong Mei Cheng ◽  
Qian Sheng Fang
Keyword(s):  
Wireless Sensor Network ◽  
Sensor Network ◽  
Information Acquisition ◽  
Host Computer ◽  
Acquisition System ◽  
Wireless Sensor ◽  
Hardware Cost ◽  
Public Building ◽  
Design And Implementation ◽  
Wireless Node

The process of building environmental information perception can be constructed with wireless sensor network (WSN) expediently. A WSN based information acquisition system for building running environment is described in this paper. The CPU of host computer in the system is Loongson2F and wireless nodes in the system are implemented as Telsob nodes. Because the price of wireless node is low, the hardware cost of the desired system is decreased evidently and the security of the desired system is enhanced because the CPU of the host is native. With those features, the application scenario of the desired system is extended widely. To verify the suitability of the using of Collection Tree Protocol (CTP) in construction of the WSN in the desired information acquisition system, the performance of the CTP based WSN deployed in public building space for environment information acquiring are tested and solutions for some key problems in the construction and the maintenance of the CTP based WSN are given in this paper too.

IMPLEMENTING FAST FOURIER TRANSFORMS ON DISTRIBUTED-MEMORY MULTIPROCESSSORS USING DATA REDISTRIBUTIONS

1994 ◽  
Vol 04 (04) ◽  
pp. 477-488 ◽  
Author(s):  
S.K.S. GUPTA ◽  
C.-H. HUANG ◽  
P. SADAYAPPAN ◽  
R.W. JOHNSON
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Distributed Memory ◽  
Fourier Transforms ◽  
Experimental Performance ◽  
Minimum Number ◽  
Data Redistribution ◽  
Using Data ◽  
Performance Results ◽  
Fft Algorithms

Implementations of various fast Fourier transform (FFT) algorithms are presented for distributed-memory multiprocessors. These algorithms use data redistribution to localize the computation. The goal is to optimize communication cost by using a minimum number of redistribution steps. Both analytical and experimental performance results on the Intel iPSC/860 system are presented.

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