A 12-bit fully differential SAR ADC with dynamic latch comparator for portable physiological monitoring applications

2011 ◽  
Author(s):  
Li Yu ◽  
Jingyong Zhang ◽  
Lei Wang ◽  
Jianguo Lu
Keyword(s):  
Sar Adc ◽  
Physiological Monitoring ◽  
Fully Differential ◽  
Monitoring Applications

The Analysis on the Parasitic Capacitors Effect of the Fully Differential Architecture of SAR ADC

2010 ◽  
Vol 20-23 ◽  
pp. 342-345
Author(s):  
Lei Sun ◽  
Qin Yuan Dai ◽  
Chuang Chuan Lee ◽  
Gao Shuai Qiao
Keyword(s):  
Theoretical Basis ◽  
Sar Adc ◽  
Common Mode ◽  
Fully Differential ◽  
Differential Structure ◽  
The Difference ◽  
The Relationship

This paper presents an analysis on the parasitic capacitors effect of the fully differential architecture to provide common-mode rejection. The parasitic capacitors of differential comparator inputs has no effect on the resolution, however, the difference of comparator input parasitic capacitors may has great effect on the resolution. The relationship between the unity capacitor and the parasitic capacitors of the differential comparator inputs is analyzed by giving precise theoretical demonstration. Therefore, a theoretical basis is provided for designers to choose appropriate unity capacitor, process and layout in the design of SAR SAD with fully differential structure.

scholarly journals Augmentation of Dispersion Entropy for Handling Missing and Outlier Samples in Physiological Signal Monitoring

Entropy ◽  
2020 ◽  
Vol 22 (3) ◽  
pp. 319 ◽  
Author(s):  
Evangelos Kafantaris ◽  
Ian Piper ◽  
Tsz-Yan Milly Lo ◽  
Javier Escudero
Keyword(s):  
Time Series ◽  
Wearable Devices ◽  
Physiological Monitoring ◽  
Disruptive Effect ◽  
Respiratory Impedance ◽  
Common Occurrence ◽  
Original Algorithm ◽  
Physiological Signal ◽  
Monitoring Applications ◽  
Improved Performance

Entropy quantification algorithms are becoming a prominent tool for the physiological monitoring of individuals through the effective measurement of irregularity in biological signals. However, to ensure their effective adaptation in monitoring applications, the performance of these algorithms needs to be robust when analysing time-series containing missing and outlier samples, which are common occurrence in physiological monitoring setups such as wearable devices and intensive care units. This paper focuses on augmenting Dispersion Entropy (DisEn) by introducing novel variations of the algorithm for improved performance in such applications. The original algorithm and its variations are tested under different experimental setups that are replicated across heart rate interval, electroencephalogram, and respiratory impedance time-series. Our results indicate that the algorithmic variations of DisEn achieve considerable improvements in performance while our analysis signifies that, in consensus with previous research, outlier samples can have a major impact in the performance of entropy quantification algorithms. Consequently, the presented variations can aid the implementation of DisEn to physiological monitoring applications through the mitigation of the disruptive effect of missing and outlier samples.

scholarly journals 14-Bit Fully Differential SAR ADC with PGA Used in Readout Circuit of CMOS Image Sensor

2021 ◽  
Vol 2021 ◽  
pp. 1-17
Author(s):  
Xiaowei Zhang ◽  
Wei Fan ◽  
Jianxiong Xi ◽  
Lenian He
Keyword(s):  
Sampling Rate ◽  
Cmos Image Sensor ◽  
Image Sensor ◽  
Sar Adc ◽  
Total Power ◽  
Cmos Process ◽  
Readout Circuit ◽  
Fully Differential ◽  
Total Power Consumption ◽  
The Impact

This paper proposes a 14-bit fully differential Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) with a programmable gain amplifier (PGA) used in the readout circuit of CMOS image sensor (CIS). SAR ADC adopts two-step scaled-reference voltages to realize 14-bit conversion, aimed at reducing the scale of capacitor array and avoiding using calibration to mitigate the impact of offset and mismatch. However, the reference voltage self-calibration algorithm is applied on the design to guarantee the precision of reference voltages, which affects the results of conversion. The three-way PGA provides three types of gains: 3x, 4x, and 6x, and samples at the same time to get three columns of pixel signal and increase the system speed. The pixel array of the mentioned CIS is 1026 × 1024 , and the pixel pitch is 12.5   μ m × 12.5   μ m . The prototype chip is fabricated in the 180 nm CMOS process, and both digital and analog voltages are 3.3 V. The total area of the chip is 6.25 × 18.38  mm2. At 150 kS/s sampling rate, the SNR of SAR ADC is 71.72 dB and the SFDR is 82.91 dB. What is more, the single SAR ADC consumes 477.2 uW with the 4.8 V PP differential input signal and the total power consumption of the CIS is about 613 mW.

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