Low-voltage power-efficient BiDPL logic design and applications

2002 ◽  
Author(s):  
M. Margala ◽  
N.G. Durdle ◽  
N.L. Rodnunsky
Keyword(s):  
Low Voltage ◽  
Logic Design ◽  
Power Efficient

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

Common Mode Feedback Circuits for Low Voltage Fully-Differential Amplifiers

2016 ◽  
Vol 25 (10) ◽  
pp. 1650124 ◽  
Author(s):  
S. Rekha ◽  
T. Laxminidhi
Keyword(s):  
Power Supply ◽  
Continuous Time ◽  
Efficient Solution ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Power Efficient ◽  
Differential Amplifiers ◽  
Fully Differential ◽  
Simulation Results

Continuous time common mode feedback (CMFB) circuits for low voltage, low power applications are proposed. Four circuits are proposed for gate/bulk-driven pseudo-differential transconductors operating on sub-1-V power supply. The circuits are validated for a bulk-driven pseudo-differential transconductor operating on 0.5[Formula: see text]V in 0.18[Formula: see text][Formula: see text]m standard CMOS technology. Simulation results reveal that the proposed CMFB circuits offer power efficient solution for setting the output common mode of the transconductors. They also load the transconductor capacitively offering capacitance of about 1[Formula: see text]fF to tens of femto farads.

scholarly journals Ultra‐low voltage, power efficient continuous‐time filters in 180 nm CMOS technology

2019 ◽  
Vol 13 (7) ◽  
pp. 988-997
Author(s):  
Rekha S. ◽  
Vasantha Moodabettu Harishchandra ◽  
Tonse Laxminidhi
Keyword(s):  
Continuous Time ◽  
Low Voltage ◽  
Cmos Technology ◽  
Power Efficient ◽  
Continuous Time Filters

Dendron engineering in self-host blue iridium dendrimers towards low-voltage-driving and power-efficient nondoped electrophosphorescent devices

2017 ◽  
Vol 53 (1) ◽  
pp. 180-183 ◽  
Author(s):  
Yang Wang ◽  
Shumeng Wang ◽  
Junqiao Ding ◽  
Lixiang Wang ◽  
Xiabin Jing ◽  
...  
Keyword(s):  
Energy Level ◽  
Low Voltage ◽  
Hole Injection ◽  
Homo Energy ◽  
Power Efficient ◽  
Homo Energy Level

Low-voltage-driving and power-efficient nondoped electrophosphorescent devices have been realized by increasing the dendron's HOMO energy level to favor effective hole injection and promote exciton formation.

Low-voltage power-efficient BiDPL adder for VLSI applications

1999 ◽  
Vol 30 (2) ◽  
pp. 193-197 ◽  
Author(s):  
Martin Margala ◽  
Nelson G Durdle
Keyword(s):  
Low Voltage ◽  
Power Efficient

Tunnel Transistor-Based Reliable and Energy Efficient Computing Architectures with Circuit and Architectural Co-Design at Low VDD

2017 ◽  
Vol 27 (03) ◽  
pp. 1850046 ◽  
Author(s):  
Sadulla Shaik ◽  
K. Sri Rama Krishna ◽  
Ramesh Vaddi
Keyword(s):  
Energy Efficiency ◽  
Energy Efficient ◽  
Low Voltage ◽  
Field Effect Transistors ◽  
Full Adder ◽  
Cmos Technology ◽  
Logic Design ◽  
Transmission Gate ◽  
Reliability Characteristics ◽  
Efficient Option

Tunnel field-effect transistors (TFETs) as low voltage device options have attracted recent attention for energy efficient circuit designs with CMOS technology scaling. This paper presents the circuit and architectural co-design approach for designing reliable and energy efficient architectures (adder cells) for new computing platforms at supply voltages. At circuit level TFET-based 28-transistor static logic design (28T) and 24-transistor transmission gate logic design (24T) have been explored. At architectural level, multiplexer (MUX)-based 22-transistor full adder design (22T) is proposed. Performance of TFET-based architectures have also been benchmarked with 20[Formula: see text]nm double gate Si FinFET technology. It has been seen that with FinFET technology 24T design is not effective in terms of energy efficiency and reliability (due to the large leakage currents in transmission gate logic topology). 28T design is the best in reliability perspective (in terms of reduced over shoots, full logic swing and reduced glitch duration etc.) and 22T design to be energy efficient option. It has been demonstrated in this paper that TFET’s steep slope characteristics enable the 24T design to have similar reliability characteristics like 28T design and energy efficiency like 22T design. TFET-based 22T design has [Formula: see text]91% smaller energy delay product (EDP) and [Formula: see text]84.4% less power delay product (PDP) in comparison to the low threshold voltage (LVT) FinFET 22T design at 0.2[Formula: see text]V VDD.

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