scholarly journals A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Chi Xu ◽  
Yu Jin ◽  
Duli Yu
Keyword(s):  
Fractional Order ◽  
Analog Circuit ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Integer Order ◽  
Noise Characteristics ◽  
Chip Testing ◽  
Sigma Delta Adc

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

scholarly journals A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 372 ◽  
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Xiaowei Liu
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Multi Stage ◽  
Sigma Delta Adc

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

Architectural Design and Simulation of a Fourth-Order Sigma-Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 723-727
Author(s):  
Wen Jie Fan ◽  
Qiu Ye Lv ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Fourth Order ◽  
Architectural Design ◽  
Simple Structure ◽  
Dynamic Range ◽  
Sampling Frequency ◽  
System Level ◽  
Noise Shaping ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Sigma Delta Adc

Sigma-delta ADC outperforms the Nyquist ADC in precision and robustness by using oversampling and noise shaping. A fourth-order sigma-delta modulator of input feedforward architecture is designed and simulated in system-level. Input feedforward architecture has advantages of low output swing of integrators and simple structure. Proper circuit parameters are also presented in this paper. The simulation revealed that the modulator achieves 109 dB dynamic range in a signal bandwidth of 1 KHz with a sampling frequency of 250 KHz.

scholarly journals Second-order sigma-delta modulator in standard cmos technology

2004 ◽  
Vol 1 (3) ◽  
pp. 37-44 ◽  
Author(s):  
Dragisa Milovanovic ◽  
Milan Savic ◽  
Miljan Nikolic
Keyword(s):  
Dynamic Range ◽  
Cmos Technology ◽  
Second Order ◽  
Clock Frequency ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Power Meter ◽  
Sampling Ratio

As a part of wider project sigma-delta modulator was designed. It represents an A/D part of a power meter IC. Requirements imposed were: SNDR and dynamic range > 50 dB for maximum input swing of 250 mV differential at 50 Hz. Over sampling ratio is 128 with clock frequency of 524288 Hz which gives bandwidth of 2048 Hz. Circuit is designed in 3.3 V supply standard CMOS 0.35 ?m technology.

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

2019 ◽  
Vol 29 (07) ◽  
pp. 2050108
Author(s):  
Di Li ◽  
Chunlong Fei ◽  
Qidong Zhang ◽  
Yani Li ◽  
Yintang Yang
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Quantization Noise ◽  
Cmos Process ◽  
Noise Shaping ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

A 5-mW sigma-delta modulator with 84-dB dynamic range for GSM/EDGE

2002 ◽  
Vol 37 (1) ◽  
pp. 2-10 ◽  
Author(s):  
O. Oliaei ◽  
P. Clement ◽  
P. Gorisse
Keyword(s):  
Dynamic Range ◽  
Sigma Delta Modulator ◽  
Sigma Delta
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