This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.
This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.
A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
