A Class-AB Bulk-Driven Amplifier with Enhanced Transconductance Using Quasi-Floating Gate Method

This paper presents a supper class-AB adaptive biasing bulk-driven amplifier for ultra-low-power applications. In the proposed structure, two bulk-driven flipped voltage follower (FVF) cells are reconfigured as nonlinear tail currents using quasi-floating gate method to enhance transconductance and slew rate. In addition, two idle current controllers are employed as common source amplifiers to provide a supper class-AB structure without increasing total current consumption. The proposed structure is simulated in 0.18-[Formula: see text]m CMOS technology at 0.5[Formula: see text]V supply with 35[Formula: see text]nW power budget. The results show a 57.9[Formula: see text]dB DC gain, 8.8[Formula: see text]kHz gain bandwidth and 38.2[Formula: see text]V/ms slew rate for the proposed amplifier.

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A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

Ingeniería e Investigación ◽

10.15446/ing.investig.v37n2.62625 ◽

2017 ◽

Vol 37 (2) ◽

pp. 82-88 ◽

Cited By ~ 1

Author(s):

Juan Jesus Ocampo-Hidalgo ◽

Iván Vázquez-Álvarez ◽

Sergio Sandoval-Perez ◽

Rodolfo Garcia-Lozano ◽

Marco Gurrola-Navarro ◽

...

Keyword(s):

Low Voltage ◽

Harmonic Distortion ◽

Main Idea ◽

Cmos Technology ◽

Floating Gate ◽

Class Ab ◽

Flipped Voltage Follower ◽

Micro Power ◽

Voltage Follower ◽

Analog Voltage

This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

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Floating-Gate MOSFET based Class-AB Flipped Voltage Follower Cell

2020 International Conference on Computational Performance Evaluation (ComPE) ◽

10.1109/compe49325.2020.9200011 ◽

2020 ◽

Author(s):

Caffey Jindal ◽

Rishikesh Pandey ◽

Arvind Thakur

Keyword(s):

Floating Gate ◽

Class Ab ◽

Flipped Voltage Follower ◽

Voltage Follower

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High slew rate and low output resistance class-AB flipped voltage follower cell with increased current driving capability

Sadhana ◽

10.1007/s12046-020-01350-0 ◽

2020 ◽

Vol 45 (1) ◽

Author(s):

CAFFEY JINDAL ◽

RISHIKESH PANDEY

Keyword(s):

Slew Rate ◽

Output Resistance ◽

Class Ab ◽

Flipped Voltage Follower ◽

Voltage Follower ◽

Driving Capability

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High Performance CMOS Current Mirror Using Class-AB Level Shifted Bulk Driven Flipped Voltage Follower Cell

Journal of Circuits System and Computers ◽

10.1142/s0218126619501408 ◽

2019 ◽

Vol 28 (08) ◽

pp. 1950140

Author(s):

Caffey ◽

Rishikesh Pandey

Keyword(s):

Supply Voltage ◽

Tracking Error ◽

Cmos Technology ◽

Current Mirror ◽

Design Environment ◽

Output Resistance ◽

Class Ab ◽

Flipped Voltage Follower ◽

Voltage Follower ◽

High Output

This paper presents a novel current mirror structure based on level shifted class-AB flipped voltage follower cell, which operates at the supply voltage of 1.2[Formula: see text]V. The level shifted class-AB flipped voltage follower cell and regulated cascode structure are used at the input and the output stages to achieve low input resistance and very high output resistance, respectively. A comparison of performance parameters of the proposed current mirror with existing structures shows that the proposed current mirror has a very less current tracking error of 0.99%, high output resistance of 18.7[Formula: see text]M[Formula: see text], wide bandwidth of 239.245[Formula: see text]MHz and low power dissipation of 104[Formula: see text][Formula: see text]W. The proposed circuit has been simulated in Cadence virtuoso analog design environment and layout of the proposed circuit has been designed in Cadence virtuoso layout XL editor using BSIM3V3 180[Formula: see text]nm CMOS technology. The post-layout simulation results have also been presented to demonstrate the effectiveness of the proposed circuit.

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