Convergence of SoC architecture and semiconductor manufacturing through AI/ML systems

2021 ◽  
Author(s):  
Srinivas Bodapati ◽  
Pushkar Ranade ◽  
Ramune Nagisetty
Keyword(s):  
Semiconductor Manufacturing

NanoProbing on 7 nm FinFET Devices in an SRAM Array: Challenges and Solutions

2019 ◽  
Author(s):  
Anqi Qiu ◽  
William Lowe ◽  
Mridul Arora
Keyword(s):  
Manufacturing Process ◽  
Semiconductor Manufacturing

Abstract Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

A Distributed-Ledger, Edge-Computing Architecture for Automation and Computer Integration in Semiconductor Manufacturing

2020 ◽  
pp. 13-29
Author(s):  
Da-Yin Liao
Keyword(s):  
Semiconductor Manufacturing ◽  
Manufacturing Systems ◽  
Edge Computing ◽  
Legacy Systems ◽  
Software Framework ◽  
Computer Integration ◽  
Computing Architecture ◽  
Disruptive Technologies ◽  
Distributed Ledger ◽  
Operational Structure

Contemporary 300mm semiconductor manufacturing systems have highly automated and digitalized cyber-physical integration. They suffer from the profound problems of integrating large, centralized legacy systems with small islands of automation. With the recent advances in disruptive technologies, semiconductor manufacturing has faced dramatic pressures to reengineer its automation and computer integrated systems. This paper proposes a Distributed-Ledger, Edge-Computing Architecture (DLECA) for automation and computer integration in semiconductor manufacturing. Based on distributed ledger and edge computing technologies, DLECA establishes a decentralized software framework where manufacturing data are stored in distributed ledgers and processed locally by executing smart contracts at the edge nodes. We adopt an important topic of automation and computer integration for semiconductor research &development (R&D) operations as the study vehicle to illustrate the operational structure and functionality, applications, and feasibility of the proposed DLECA software framework.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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