FIRestarter: Practical Software Crash Recovery with Targeted Library-level Fault Injection

<div> <p>Site-specific protein modification is a widely-used strategy to attach drugs, imaging agents, or other useful small molecules to protein carriers. N-terminal modification is particularly useful as a high-yielding, site-selective modification strategy that can be compatible with a wide array of proteins. However, this modification strategy is incompatible with proteins with buried or sterically-hindered N termini, such as virus-like particles like the well-studied MS2 bacteriophage coat protein. To assess VLPs with improved compatibility with these techniques, we generated a targeted library based on the MS2-derived protein cage with N-terminal proline residues followed by three variable positions. We subjected the library to assembly, heat, and chemical selections, and we identified variants that were modified in high yield with no reduction in thermostability. Positive charge adjacent to the native N terminus is surprisingly beneficial for successful extension, and over 50% of the highest performing variants contained positive charge at this position. Taken together, these studies described nonintuitive design rules governing N-terminal extensions and identified successful extensions with high modification potential.</p> </div>

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A Manual Diagnosis Approach Using Targeted Fault Injection and Fault Simulation to Extend ATPG Diagnostic Resolution in Localizing Faults

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0419 ◽

2019 ◽

Author(s):

Rommel Estores ◽

Karo Vander Gucht

Keyword(s):

Fault Injection ◽

Fault Simulation ◽

Fault Localization ◽

Pattern Generation ◽

Test Coverage ◽

Actual Case ◽

Electrical Failure ◽

Starting Point ◽

Diagnostic Resolution ◽

Diagnosis Approach

Abstract This paper discusses a creative manual diagnosis approach, a complementary technique that provides the possibility to extend Automatic Test Pattern Generation (ATPG) beyond its own limits. The authors will discuss this approach in detail using an actual case – a test coverage issue where user-generated ATPG patterns and the resulting ATPG diagnosis isolated the fault to a small part of the digital core. However, traditional fault localization techniques was unable to isolate the fault further. Using the defect candidates from ATPG diagnosis as a starting point, manual diagnosis through fault Injection and fault simulation was performed. Further fault localization was performed using the ‘not detected’ (ND) and/or ‘detected’ (DT) fault classes for each of the available patterns. The result has successfully deduced the defect candidates until the exact faulty net causing the electrical failure was identified. The ability of the FA lab to maximize the use of ATPG in combination with other tools/techniques to investigate failures in detail; is crucial in the fast root cause determination and, in case of a test coverage, aid in having effective test screen method implemented.

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Timing Sensitivity Analysis of Logical Nodes in Scan Design Integrated Circuits by Pulsed Diode Laser Stimulation

ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2008p0180 ◽

2008 ◽

Author(s):

T. Kiyan ◽

C. Boit ◽

C. Brillert

Keyword(s):

Laser Pulse ◽

Integrated Circuits ◽

Continuous Wave ◽

Fault Injection ◽

Scan Design ◽

Flip Flop ◽

Laser Stimulation ◽

Scan Chain ◽

P Type ◽

Scan Pattern

Abstract In this paper, a methodology based upon laser stimulation and a comparison of continuous wave and pulsed laser operation will be presented that localizes the fault relevant sites in a fully functional scan chain cell. The technique uses a laser incident from the backside to inject soft faults into internal nodes of a master-slave scan flip-flop in consequence of localized photocurrent. Depending on the illuminated type of the transistors (n- or p-type), injection of a logic ‘0’ or ‘1’ into the master or the slave stage of a flip-flop takes place. The laser pulse is externally triggered and can easily be shifted to various time slots in reference to clock and scan pattern. This feature of the laser diode allows triggering the laser pulse on the rising or the falling edge of the clock. Therefore, it is possible to choose the stage of the flip-flop in which the fault injection should occur. It is also demonstrated that the technique is able to identify the most sensitive signal condition for fault injection with a better time resolution than the pulse width of the laser, a significant improvement for failure analysis of integrated circuits.

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