Warpage and Thermal Stress under Thermal Cycling Test in SiC and Si Power Device Structures Using Direct Chip-Bonding with Ag Sintered Layer on Cu Plate

2018 ◽  
Author(s):  
Masaki Kanemoto ◽  
Masaaki Aoki ◽  
Akihiro Mochizuki ◽  
Yoshio Murakami ◽  
Mutsuharu Tsunoda ◽  
...  
Keyword(s):  
Thermal Stress ◽  
Thermal Cycling ◽  
Power Device ◽  
Thermal Cycling Test ◽  
Cycling Test ◽  
Device Structures ◽  
Sintered Layer

A thermal cycling test of tungsten copper bonds for divertor collector plates

1989 ◽  
Vol 9 ◽  
pp. 271-276 ◽  
Author(s):  
M. Ogawa ◽  
M. Seki ◽  
K. Fukaya ◽  
T. Horie ◽  
T. Araki
Keyword(s):  
Thermal Cycling ◽  
Thermal Cycling Test ◽  
Cycling Test

Development of low temperature sintered nano silver pastes using MO technology and resin reinforcing technology

2014 ◽  
Vol 2014 (HITEC) ◽  
pp. 000172-000177
Author(s):  
Koji Sasaki ◽  
Noritsuka Mizumura
Keyword(s):  
Shear Strength ◽  
Low Temperature ◽  
Thermal Cycling ◽  
Thick Film ◽  
Thermal Performance ◽  
Low Temperature Sintering ◽  
Thermal Cycling Test ◽  
Nano Silver ◽  
Cycling Test ◽  
Thick Film Technology

Traditional thick film technology is widely used in various electronics products. There are two type of paste based on thick film technology. Typically, over 400°C is required for high temperature sintering type which contains glass for adhesion function. It shows high electrical and thermal performance. On the other hand, 150–300°C range process is used for low temperature process type as silver epoxy. In last decade, nano silver technology shows amazing progress to address low temperature operation by low temperature sintering. This paper will discuss the results on fundamental study of newly developed nano silver pastes with unique approach which uses MO (Metallo-organic) technology and resin reinforcing technology. Nano silver pastes contain several types of dispersant as surface coating to prevent agglomeration of the particles. Various coating technique has been reported to optimize sintering performance and stability. MO technology provides low temperature sintering capability by minimizing the coating material. The nano silver pastes show high electrical and thermal performance. However, degradation of die shear strength has been found by thermal cycling test due to the fragility of porous sintered structure. To improve the mechanical property, resin reinforcing technology has been developed. By adding special resin to the pastes, the porous area is filled with the resin and the sintered structure is reinforced. Degradation of die shear strength was not found by thermal cycling test to 1000 cycles. Nano silver pastes using MO technology and resin reinforcing technology will meet lots of requirement on various thick film applications.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

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