A Novel RISC Architecture for High-Speed Floating-Point Signal Processing

Author(s):  
B. Yernaux ◽  
P.G.A. Jespers

Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.


In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.


Actuators ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 115
Author(s):  
Teemu Sillanpää ◽  
Alexander Smirnov ◽  
Pekko Jaatinen ◽  
Jouni Vuojolainen ◽  
Niko Nevaranta ◽  
...  

Non-contact rotor position sensors are an essential part of control systems in magnetically suspended high-speed drives. In typical active magnetic bearing (AMB) levitated high-speed machine applications, the displacement of the rotor in the mechanical air gap is measured with commercially available eddy current-based displacement sensors. The aim of this paper is to propose a robust and compact three-dimensional position sensor that can measure the rotor displacement of an AMB system in both the radial and axial directions. The paper presents a sensor design utilizing only a single unified sensor stator and a single shared rotor mounted target piece surface to achieve the measurement of all three measurement axes. The sensor uses an inductive measuring principle to sense the air gap between the sensor stator and rotor piece, which makes it robust to surface variations of the sensing target. Combined with the sensor design, a state of the art fully digital signal processing chain utilizing synchronous in-phase and quadrature demodulation is presented. The feasibility of the proposed sensor design is verified in a closed-loop control application utilizing a 350-kW, 15,000-r/min high-speed industrial induction machine with magnetic bearing suspension. The inductive sensor provides an alternative solution to commercial eddy current displacement sensors. It meets the application requirements and has a robust construction utilizing conventional electrical steel lamination stacks and copper winding.


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