scholarly journals Merged Floating Point Multipliers

2019 ◽  
Vol 9 (1S5) ◽  
pp. 178-181
Keyword(s):  
Signal Processing ◽  
Power Dissipation ◽  
Resource Sharing ◽  
High Speed ◽  
Literature Survey ◽  
Floating Point ◽  
Computational Time ◽  
Extensive Literature ◽  
Low Power Dissipation ◽  
Research Criteria

Floating point multipliers are extensively used in many scientific and signal processing computations, due to high speed and memory requirements of IEEE-754 floating point multipliers which prevents its implementation in many systems because of fast computations. Hence floating point multipliers became one of the research criteria. This research aims to design a new floating point multiplier that occupies less area, low power dissipation and reduces computational time (more speed) when compared to the conventional architectures. After an extensive literature survey, new architecture was recognized i.e, resource sharing Karatsuba –Ofman algorithm which occupies less area, power and increasing speed. The design was implemented in mat lab using DSP block sets, simulator tool is Xilinx Vivado.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

Design of Low Power CMOS Comparator using 180nm Technology for ADC Application

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 11-13
Author(s):  
Truptimayee Behera ◽  
Ritisnigdha Das
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
High Performance ◽  
Input Voltage ◽  
Clock Frequency ◽  
Nmos Transistor ◽  
Body Effect ◽  
Low Power Dissipation ◽  
Low Power Cmos

In our design of CMOS comparator with high performance using GPDK 180nm technology we optimize these parameters. We analyse the transient response of the schematic design and the gain is calculated in AC analysis and also we measure the power dissipation. The circuit is built by using PMOS and NMOS transistor with a body effect. A plot of phase and gain also discussed in the paper. Finally a test schematic is built and transient analysis for an input voltage of 2V is measured using Cadence virtuoso. Simulation results are presented and it shows that this design can work under high speed clock frequency 200MHz. The design has low power dissipation.

scholarly journals Design of High Speed FFT using Urdhva-Tiryagbhyam Algorithm and Karatsuba Algorithm

2020 ◽  
Vol 9 (4) ◽  
pp. 1904-1908
Keyword(s):  
Image Processing ◽  
Signal Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Execution Time ◽  
Communication Systems ◽  
High Speed ◽  
Floating Point ◽  
Calculation Algorithms ◽  
Floating Point Number

In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.

A PSPICE Fast Model for the Single Electron Transistor

2019 ◽  
pp. 08-23
Author(s):  
Lobna Osman ◽  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Electron Tunneling ◽  
Electronic Devices ◽  
Single Electron ◽  
Single Electron Transistor ◽  
Electrical Characteristics ◽  
Nanoelectronic Devices ◽  
Low Power Dissipation

Motivated by the merits of low power dissipation, ultra-small size, and high speed of many nanoelectronic devices, They have been demonstrated to ensure future progress. Single-electron devices became one of the most important nanoelectronic devices due to their interesting electrical characteristics and behavior. Many research efforts moved to describe their electrical characteristics to use them with conventional electronic devices. This paper deals with modeling and simulation of such new electronic devices. This paper presents a model for the Single Electron Transistor (SET) and its application in simulating hybrid SET/MOS ADC and DAC converters. This model uses the orthodox theory of single-electron tunneling and determines the average current through the transistor. The proposed model is more flexible that is valid for a large range of drain to source voltage, valid for single or multi-gate SET and symmetric or asymmetric SET. Finally, using this model with MOSFET transistors to realize multi-bit Analog-to-Digital Converters (ADC) and Digital-to-Analog Converters (DAC). The hybrid n-bit DAC nano-circuits are simulated for (n=4 and 8) using Orcad Capture PSPICE. The performance of the SET/MOS hybrid n-bit ADC circuits were simulated (for n=3 and 8). The results show that the transient operation of hybrid SET/MOS circuit-based DAC could successfully operate at 1000K while ADC could operate at 144K. This performance can be compared with the pure SET circuits, the proposed converter circuits have been enhanced in the drive capability and the power dissipation. Compared with the other SET/MOS hybrid circuit, the implemented converter circuits have low simulation time, high speed, high load drivability, and low power dissipation.

Double implanted bipolar high-speed gates with low-power dissipation

2005 ◽  
Author(s):  
J. Graul ◽  
H. Kaiser ◽  
N. Kokkotakis ◽  
W. Wilhelm ◽  
H. Ryssel ◽  
...  
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Low Power Dissipation

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

2013 ◽  
Vol 321-324 ◽  
pp. 2822-2827 ◽  
Author(s):  
Mao Qiang Duan ◽  
Xiao Li Huang
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
High Speed ◽  
Hardware Design ◽  
Cmos Technology ◽  
Shift Register ◽  
Vlsi Implementation ◽  
Parallel Method ◽  
Parallel Circuits ◽  
Low Power Dissipation

The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35μm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

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