Reliability investigations of large die wafer level package (part II): Impact of solder ball composition, die thickness, and polymer passivition on board level reliability

2016 ◽  
Author(s):  
Chien-An Hsieh ◽  
Markus Jarn ◽  
Yu-Chi Pai ◽  
Yi-Liang Chen ◽  
Bradford J. Factor ◽  
...  
Keyword(s):  
Solder Ball ◽  
Wafer Level ◽  
Board Level ◽  
Wafer Level Package ◽  
Board Level Reliability ◽  
Die Thickness

Investigations of Board-Level Drop Reliability of Wafer-Level Chip-Scale Packages

2006 ◽  
Vol 129 (1) ◽  
pp. 105-108 ◽  
Author(s):  
Yi-Shao Lai ◽  
Chang-Lin Yeh ◽  
Ching-Chun Wang
Keyword(s):  
Time Integration ◽  
Implicit Time ◽  
Wafer Level ◽  
Excitation Scheme ◽  
Implicit Time Integration ◽  
Parametric Studies ◽  
Support Excitation ◽  
Board Level ◽  
Board Level Reliability ◽  
Die Thickness

We present in this paper parametric studies of board-level reliability of wafer-level chip-scale packages subjected to a specific pulse-controlled drop test condition. Eighteen experiment cells, constructed by varying joint pitch, die thickness, and die size, are proposed and examined numerically. The transient analysis follows the support excitation scheme and incorporates an implicit time integration solver. Numerical results indicate that the drop reliability of the package enhances as the die thickness as well as the die size decreases. Moreover, the package with smaller solder joints and a smaller joint pitch suffers a greater drop reliability concern.

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