Design of Full Adder and Parity Generator Based on Reversible Logic

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

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Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

Journal of Bangladesh Academy of Sciences ◽

10.3329/jbas.v32i2.2431 ◽

1970 ◽

Vol 32 (2) ◽

Cited By ~ 7

Author(s):

Md Saiful Islam ◽

Zerina Begum

Keyword(s):

Fault Tolerant ◽

Logic Gate ◽

Logic Synthesis ◽

Digital Signal ◽

Full Adder ◽

Research Area ◽

Reversible Logic ◽

Hardware Complexity ◽

Fundamental Building Block ◽

Reversible Gate

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts. Keywords: Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic. doi: 10.3329/jbas.v32i2.2431 Journal of Bangladesh Academy of Sciences Vol.32(2) 2008 234-250

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Design and Analysis of Energy Efficient Reversible Logic based Full Adder

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) ◽

10.1109/mwscas.2019.8884882 ◽

2019 ◽

Author(s):

Jagadeesh Pujar ◽

Sithara Raveendran ◽

Trilochan Panigrahi ◽

M.H. Vasantha ◽

Nithin Kumar Y.B.

Keyword(s):

Energy Efficient ◽

Full Adder ◽

Reversible Logic

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Reversible logic gate implementation as switch controlled reversible full adder/subtractor

2014 IEEE International Conference on Control System, Computing and Engineering (ICCSCE 2014) ◽

10.1109/iccsce.2014.7111144 ◽

2014 ◽

Cited By ~ 3

Author(s):

Lenin Gopal ◽

Adib Kabir Chowdhury ◽

Alpha Agape Gopalai ◽

Ashutosh Kumar Singh ◽

Bakri Madon

Keyword(s):

Logic Gate ◽

Full Adder ◽

Reversible Logic

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Low Delay Based Full Adder/Subtractor by MIG and COG Reversible Logic Gate

2016 8th International Conference on Computational Intelligence and Communication Networks (CICN) ◽

10.1109/cicn.2016.120 ◽

2016 ◽

Author(s):

Jacob B. Chacko ◽

Pawan Whig

Keyword(s):

Logic Gate ◽

Full Adder ◽

Reversible Logic ◽

Low Delay

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MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT

International Journal of Quantum Information ◽

10.1142/s0219749909005523 ◽

2009 ◽

Vol 07 (05) ◽

pp. 969-989 ◽

Cited By ~ 23

Author(s):

MAJID MOHAMMADI ◽

MAJID HAGHPARAST ◽

MOHAMMAD ESHGHI ◽

KEIVAN NAVI

Keyword(s):

Genetic Algorithm ◽

Circuit Design ◽

Synthesis Method ◽

Full Adder ◽

Reversible Logic ◽

Quantum Cost ◽

The Third ◽

Modular Synthesis ◽

Minimum Number

Reversible logic and binary coded decimal (BCD) arithmetic are two concerning subjects of hardware. This paper proposes a modular synthesis method to realize a reversible BCD-full adder (BCD-FA) and subtractor circuit. We propose three approaches to design and optimize all parts of a BCD-FA circuit using genetic algorithm and don't care concept. Our first approach is based on the Hafiz's work, and the second one is based on the whole BCD-FA circuit design. In the third approach, a binary to BCD converter is presented. Optimizations are done in terms of number of gates, number of garbage inputs/outputs, and the quantum cost of the circuit. We present four designs for BCD-FA with four different goals: minimum garbage inputs/outputs, minimum quantum cost, minimum number of gates, and optimum circuit in terms of all the above parameters.

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