MINIMIZATION AND OPTIMIZATION OF REVERSIBLE BCD-FULL ADDER/SUBTRACTOR USING GENETIC ALGORITHM AND DON'T CARE CONCEPT

2009 ◽  
Vol 07 (05) ◽  
pp. 969-989 ◽  
Author(s):  
MAJID MOHAMMADI ◽  
MAJID HAGHPARAST ◽  
MOHAMMAD ESHGHI ◽  
KEIVAN NAVI
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Synthesis Method ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
The Third ◽  
Modular Synthesis ◽  
Minimum Number

Reversible logic and binary coded decimal (BCD) arithmetic are two concerning subjects of hardware. This paper proposes a modular synthesis method to realize a reversible BCD-full adder (BCD-FA) and subtractor circuit. We propose three approaches to design and optimize all parts of a BCD-FA circuit using genetic algorithm and don't care concept. Our first approach is based on the Hafiz's work, and the second one is based on the whole BCD-FA circuit design. In the third approach, a binary to BCD converter is presented. Optimizations are done in terms of number of gates, number of garbage inputs/outputs, and the quantum cost of the circuit. We present four designs for BCD-FA with four different goals: minimum garbage inputs/outputs, minimum quantum cost, minimum number of gates, and optimum circuit in terms of all the above parameters.

Design of Combinational Circuits Using Reversible Decoder in Tanner Tools

2020 ◽  
Vol 17 (4) ◽  
pp. 1743-1751
Author(s):  
R. Kannan ◽  
K. Vidhya
Keyword(s):  
Low Power ◽  
Optical Computing ◽  
Logic Gates ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Combinational Circuits ◽  
Nano Technology ◽  
Feynman Gate ◽  
Reversible Logic Gates

Reversible logic is the emerging field for research in present era. The aim of this paper is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder circuit with minimum quantum cost. Reversible decoder is designed using Fredkin gates with minimum Quantum cost. There are many reversible logic gates like Fredkin Gate, Feynman Gate, Double Feynman Gate, Peres Gate, Seynman Gate and many more. Reversible logic is defined as the logic in which the number output lines are equal to the number of input lines i.e., the n-input and k-output Boolean function F(X1,X2,X3, ...,Xn) (referred to as (n,k) function) is said to be reversible if and only if (i) n is equal to k and (ii) each input pattern is mapped uniquely to output pattern. The gate must run forward and backward that is the inputs can also be retrieved from outputs. When the device obeys these two conditions then the second law of thermo-dynamics guarantees that it dissipates no heat. Fan-out and Feed-back are not allowed in Logical Reversibility. Reversible Logic owns its applications in various fields which include Quantum Computing, Optical Computing, Nano-technology, Computer Graphics, low power VLSI etc. Reversible logic is gaining its own importance in recent years largely due to its property of low power consumption. The comparative study in terms of garbage outputs, Quantum Cost, numbers of gates are also presented. The Circuit has been implemented and simulated using Tannaer tools v15.0 software.

scholarly journals Design Methodologies for Reversible Logic Based Barrel Shifters

2015 ◽  
Vol 25 (02) ◽  
pp. 1650003
Author(s):  
Saurabh Kotiyal ◽  
Himanshu Thapliyal
Keyword(s):  
Optical Computing ◽  
Reversible Logic ◽  
The Other ◽  
Quantum Cost ◽  
Design Methodologies ◽  
Fredkin Gate ◽  
Barrel Shifter ◽  
Minimum Number ◽  
Feynman Gate ◽  
Ancilla Inputs

Barrel shifter is an integral component of processor datapaths in computing systems since it can shift and rotate multiple bits in a single cycle. Furthermore, reversible logic has applications in emerging computing paradigms such as quantum computing, quantum dot cellular automata, optical computing, etc. In this work, we propose efficient methodologies for designing reversible barrel shifters. The proposed methodologies are designed using Fredkin gate and Feynman gate (FG). The Fredkin gate is used because it can implement a 2:1 MUX with minimum quantum cost, minimum number of ancilla inputs and garbage outputs, and the Feynman gate is used to avoid a fanout since a fanout is not allowed in reversible logic. In the existing literature, design methodologies are limited to the design of a ([Formula: see text]) reversible left rotator that can only perform the left rotate operation. This work explores the other primary functionalities of a reversible barrel shifter such as the design of a reversible: (i) logical right shifter, (ii) universal right shifter that supports logical right shifter, arithmetic right shifter and right rotate operation, (iii) bidirectional logical shifter and (iv) universal bidirectional shifter that supports bidirectional logical and arithmetic shifter and rotate operations. The other types of reversible barrel shifters can also be easily designed by making minor modifications in the proposed methodologies. The proposed design methodologies are generic in nature and can be implemented using any barrel shifter of ([Formula: see text]) size, where n and k are the number of data bits and shift value, respectively. In order to minimize the number of ancilla inputs and garbage outputs, strategies such as the implementation of an n number of 2:1 MUXes as a chain of n Fredkin gates and the mapping of the two different 2:1 MUXes that are controlled by a common control signal but having the swapped controlled signals on a single Fredkin gate, are utilized. The design methodologies are evaluated in terms of the number of garbage outputs, the number of ancilla inputs and quantum cost. For a ([Formula: see text]) reversible barrel shifter, the relations between the varying values of n and k and their impact on the number of garbage outputs, the number of ancilla inputs and quantum cost are also established to help the designers in choosing an efficient barrel shifter according to their design needs.

A NOVEL REVERSIBLE ZS GATE AND ITS APPLICATION FOR OPTIMIZATION OF QUANTUM ADDER CIRCUITS

2011 ◽  
Vol 20 (06) ◽  
pp. 1107-1129 ◽  
Author(s):  
RIGUI ZHOU ◽  
YANG SHI ◽  
MANQUN ZHANG ◽  
HUI'AN WANG
Keyword(s):  
Lower Bounds ◽  
Full Adder ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Reversible Gate ◽  
No Wait

The key of optimizing quantum reversible logic lies in automatically constructing quantum reversible logic circuits with the minimal quantum cost. This paper constructs a 4 × 4 reversible gate called ZS gate to build quantum full adder. At the same time, a novel reversible No-Wait-Carry adder (or carry skip adder) by using ZSCGPD based on ZS gate with the least cost is also designed. The adder circuit using the proposed ZSCGPD is much better and optimized than other researchers' counterparts both in terms of garbage outputs, number and kind of reversible gates, and quantum cost. In order to show the efficiency of the proposed designs, lower bounds of the reversible carry skip adder in terms of garbage outputs and quantum cost are proposed as well.

Optimized parity preserving quantum reversible full adder/subtractor

2016 ◽  
Vol 14 (03) ◽  
pp. 1650019 ◽  
Author(s):  
Majid Haghparast ◽  
Ali Bolhassani
Keyword(s):  
Emerging Technologies ◽  
Internal Heat ◽  
Cost Effective ◽  
Full Adder ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Reversible Circuits

Reversible logic is one of the indispensable aspects of emerging technologies for reducing physical entropy gain, since reversible circuits do not lose information in the form of internal heat during computation. This paper aimed to initiate constructing parity preserving reversible circuits. A novel parity preserving reversible block, HB is presented. Then a new design of a cost-effective parity preserving reversible full adder/subtractor (PPFA/S) is proposed. Next, we suggested a new parity preserving binary to BCD converter. Finally, we proposed new realization of parity preserving reversible BCD adder. The proposed designs are cost-effective in terms of quantum cost and delay. All the scales are in the NANO-metric area.

scholarly journals Evolutionary Design of Combinational Logic Circuits

2004 ◽  
Vol 8 (5) ◽  
pp. 507-513 ◽  
Author(s):  
Cecília Reis ◽  
◽  
J. A. Tenreiro Machado ◽  
J. Boaventura Cunha ◽  
Keyword(s):  
Genetic Algorithm ◽  
Full Adder ◽  
Logic Circuits ◽  
Evolutionary Design ◽  
Combinational Logic ◽  
Case Examples ◽  
Parity Checker ◽  
Minimum Number ◽  
Combinational Logic Circuits

This paper proposes a genetic algorithm for designing combinational logic circuits and studies four different case examples: 2-to-1 multiplexer, one-bit full adder, four-bit parity checker and a two-bit multiplier. The objective of this work is to generate a functional circuit with the minimum number of gates.

scholarly journals Speciation-based genetic algorithm in analog circuit design

2016 ◽  
Vol 24 ◽  
pp. 1022-1033
Author(s):  
Hasari KARCİ ◽  
Gülay TOHUMOĞLU ◽  
Arif NACAROĞLU
Keyword(s):  
Genetic Algorithm ◽  
Circuit Design ◽  
Analog Circuit ◽  
Analog Circuit Design

scholarly journals Detection of Yeast-like Symbionts in Brown Planthopper Reared on Different Resistant Rice Varieties Combining DGGE and Absolute Quantitative Real-Time PCR

Insects ◽  
2022 ◽  
Vol 13 (1) ◽  
pp. 85
Author(s):  
Chengling Lai ◽  
Yun Hou ◽  
Peiying Hao ◽  
Kun Pang ◽  
Xiaoping Yu
Keyword(s):  
Real Time ◽  
Real Time Pcr ◽  
Brown Planthopper ◽  
Nilaparvata Lugens ◽  
Quantitative Real Time Pcr ◽  
Nymphal Instar ◽  
Rice Varieties ◽  
Development Stages ◽  
The Third ◽  
Minimum Number

The brown planthopper (BPH), Nilaparvata lugens, is a serious pest of rice throughout Asia. Yeast-like symbionts (YLS) are endosymbionts closely linked with the development of BPH and the adapted mechanism of BPH virulence to resistant plants. In this study, we used semi-quantitative DGGE and absolute quantitative real-time PCR (qPCR) to quantify the number of the three YLS strains (Ascomycetes symbionts, Pichia-like symbionts, and Candida-like symbionts) that typically infect BPH in the nymphal stages and in newly emerged female adults. The quantities of each of the three YLS assessed increased in tandem with the developing nymphal instar stages, peaking at the fourth instar stage, and then declined significantly at the fifth instar stage. However, the amount of YLS present recovered sharply within the emerging adult females. Additionally, we estimated the quantities of YLS for up to eight generations after their inoculation onto resistant cultivars (Mudgo, ASD7, and RH) to reassociate the dynamics of YLS with the fitness of BPH. The minimum number of each YLS was detected in the second generation and gradually increased from the third generation with regard to resistant rice varieties. In addition, the Ascomycetes symbionts of YLS were found to be the most abundant of the three YLS strains tested for all of the development stages of BPH.

scholarly journals Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

2020 ◽  
Vol 39 (5) ◽  
pp. 1099-1116
Author(s):  
Kamaraj Arunachalam ◽  
Marichamy Perumalsamy ◽  
Kaviyashri K. Ponnusamy
Keyword(s):  
Fault Tolerance ◽  
Cost Optimization ◽  
Logic Circuits ◽  
Reversible Logic ◽  
Quantum Cost
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