scholarly journals Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder

1970 ◽  
Vol 32 (2) ◽  
Author(s):  
Md Saiful Islam ◽  
Zerina Begum
Keyword(s):  
Fault Tolerant ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Digital Signal ◽  
Full Adder ◽  
Research Area ◽  
Reversible Logic ◽  
Hardware Complexity ◽  
Fundamental Building Block ◽  
Reversible Gate

Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. This paper presents a new 4*4 parity preserving reversible logic gate, IG. The proposed parity preserving reversible gate can be used to synthesize any arbitrary Boolean function. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. It is shown that a fault tolerant reversible full adder circuit can be realized using only two IGs. The proposed fault tolerant full adder (FTFA) is used to design other arithmetic logic circuits for which it is used as the fundamental building block. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts. Keywords: Reversible Logic, Parity Preserving Reversible Gate, IG Gate, FTFA and Carry Skip Logic. doi: 10.3329/jbas.v32i2.2431 Journal of Bangladesh Academy of Sciences Vol.32(2) 2008 234-250

CHARACTERIZATION, TEST AND LOGIC SYNTHESIS OF NOVEL CONSERVATIVE AND REVERSIBLE LOGIC GATES FOR QCA

2010 ◽  
Vol 09 (03) ◽  
pp. 201-214 ◽  
Author(s):  
KUNAL DAS ◽  
DEBASHIS DE
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Synthesis ◽  
Vlsi Design ◽  
Logic Gates ◽  
Reversible Logic ◽  
Computing Paradigm ◽  
Scale Integration

Quantum dot cellular automaton (QCA) is an emerging technology in the field of nanotechnology. Reversible logic is emerging as a promising computing paradigm with applications in low-power quantum computing and QCA in the field of very large scale integration (VLSI) design. In this paper, we worked on conservative logic gate (CLG) and reversible logic gate (RLG). We examined that RLG and CLG are two classes of logic family intersecting each other. The intersection of RLG and CLG is parity preserving reversible (PPR) or conservative reversible logic gate (CRLG). We proposed in this paper, three algorithms to find different k × k RLG as well as CLG. Here, we demonstrate only the most promising two proposed gates of different categories. We compared the results with that of the previous Fredkin gate. The result shows that logic synthesis using above two gates will be a promising step towards the low-power QCA design era. We have shown a parity preserving approach to design all possible CLG. We also discuss a coupled Majority–minority-Voter (MmV) in a single nanostructure, dual outputs are driven simultaneously. This MmV gate is used for implementing n variables symmetric functions, testing the conservative gates as we explained that parity must be preserved if Majority and Minority output are same as input as well as output of CLG.

Reversible logic synthesis for minimization of full-adder circuit

2003 ◽  
Author(s):  
Hafiz Md Hasan Babu ◽  
Md Rafiqul Islam ◽  
Ahsan Raja Chowdhury ◽  
Syed Mostahed Ali Chowdhury
Keyword(s):  
Logic Synthesis ◽  
Full Adder ◽  
Reversible Logic ◽  
Reversible Logic Synthesis

The Quantum Cost Optimized Design of 2:4 Decoder Using the New Reversible Logic Block

2020 ◽  
Vol 12 (3) ◽  
pp. 146-148
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Arup K. Bhattacharjee ◽  
Anita Pal
Keyword(s):  
Logic Gate ◽  
Quantum Circuit ◽  
Reversible Logic ◽  
Optimized Design ◽  
Quantum Cost ◽  
Constant Input ◽  
Logic Block ◽  
Reversible Gate ◽  
Garbage Output

Aim and Objective: This paper presents the quantum cost, garbage output, constant input and number of reversible gate optimized 2:4 decoder using 4×4 new reversible logic gate which is named as reversible decoder block or RD block. Method: The proposed block is implemented with a quantum circuit and quantum cost of the proposed RD block is 8. The proposed decoder can be designed using only one new proposed block. Results and Conclusion: The quantum cost, garbage output, constant input and gate number of the proposed 2:4 decoder is 9, 0, 2 and 1 which is better w.r.t previously reported work. The improvement % of quantum cost, garbage output, constant input and number of gates are 12.5 – 77.148 %, 100 %, 33.33 – 75 % and 0 – 85.71%.

Iterative Construct of Reversible Network Based on Cascade Operation

2013 ◽  
Vol 798-799 ◽  
pp. 419-422
Author(s):  
Yi Qing Zhang ◽  
Zhi Jin Guan ◽  
Can Gang Lu ◽  
Jin Feng He
Keyword(s):  
Logic Gate ◽  
Logic Synthesis ◽  
Reversible Logic ◽  
Algorithm Analysis ◽  
Balance Function ◽  
Important Decision ◽  
Developing Area ◽  
Reversible Logic Synthesis

Reversible logic synthesis has become a fast developing area. In order to construct reversible logic gate network, this paper presents an algorithm of iterative construct reversible network by cascade operation. The cascade operation was implemented with Boolean permutation. We proposed two important decision condition of Boolean permutation, and changed to choose balance function of suffice Boolean permutation condition for the problem of construct reversible network. The result of algorithm analysis show that it is can be implemented fleetly.

Design of BCD to Excess-3 code converter circuit with optimized quantum cost, garbage output and constant input using reversible gate

2018 ◽  
Vol 16 (07) ◽  
pp. 1850061 ◽  
Author(s):  
Heranmoy Maity ◽  
Arindam Biswas ◽  
Anita Pal ◽  
Anup Kumar Bhattacharjee
Keyword(s):  
Logic Gate ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Constant Input ◽  
Code Converter ◽  
Reversible Circuit ◽  
Reversible Gate ◽  
Garbage Output ◽  
Feynman Gate

In this paper, we have proposed the optimized BCD to Excess-3 code converter using reversible logic gate. BCD to Excess-3 code can be generated by adding “0011” to BCD number, but in the proposed work, addition is not required. The proposed reversible circuit can be designed using peres gate, Feynman gate and NOT gate optimized quantum cost, garbage output and constant input. The quantum cost (QC), garbage output and constant input of proposed reversible BCD to Excess-3 code converter are respectively 14, 1 and 1 which is better with respect to previously reported results. The improvement is, respectively 0–65%, 66.66–91.66% and 66.66–87.5%.

scholarly journals A review on reversible logic gates

2020 ◽  
Vol 12 (1) ◽  
pp. 242-250
Author(s):  
B.Y. Galadima ◽  
G.S.M. Galadanci ◽  
A. Tijjani ◽  
M. Ibrahim
Keyword(s):  
Digital Signal ◽  
Logic Gates ◽  
Propagation Delay ◽  
Reversible Logic ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Nano Technology ◽  
Reversible Circuits ◽  
Comparative Review ◽  
Reversible Logic Gates

In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.   Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic,

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