Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression

2012 ◽  
Author(s):  
Yi He ◽  
Maolin Guan ◽  
Chunyuan Zhang ◽  
Tian Tian ◽  
Qianming Yang
Keyword(s):  
Memory Design ◽  
Stream Architecture ◽  
On Chip ◽  
Instruction Memory

scholarly journals 6 Transistors and 1 Memristor based Memory Cell

2020 ◽  
Vol 9 (1) ◽  
pp. 42
Author(s):  
Kazi Fatima Sharif ◽  
Satyendra N. Biswas
Keyword(s):  
Memory Cell ◽  
Silicon Area ◽  
Memory Design ◽  
Hybrid Memory ◽  
Noise Margin ◽  
Proposed Model ◽  
New Type ◽  
On Chip ◽  
Stable Memory ◽  
Nmos Transistors

Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.<br />The proposed memory cell is very stable during successive read operates and<br />comparatively faster and also occupies less amount of silicon area. The<br />stability of the data during successive read operation and noise margin are in<br />the promising range. Extensive simulation results using LTspice and<br />Cadence software tools demonstrate the validity and competency of the<br />proposed model.

Implementing and Optimizing DES on Stream Processor

2012 ◽  
Vol 532-533 ◽  
pp. 714-718
Author(s):  
Liu Yang ◽  
Xiao Qiang Ni ◽  
Heng Zhu Liu
Keyword(s):  
Programming Model ◽  
Data Locality ◽  
The Novel ◽  
Stream Processor ◽  
Stream Programming ◽  
Stream Architecture ◽  
On Chip

Processors using stream architecture can make good use of the on-chip resources and explore the data locality and parallelism. DES algorithm is one of the most popular cipher algorithms. This paper proposes the novel implementation of DES algorithm on stream architecture based on both stream programming model and DES algorithm and the speedup is 1.27 times.

Viewing Context Adaptive On-Chip Video Memory

2015 ◽  
Vol 2015 (1) ◽  
pp. 000216-000219
Author(s):  
Dongliang Chen ◽  
Jinhui Wang ◽  
Na Gong
Keyword(s):  
Mobile Phones ◽  
Design Methodology ◽  
Low Cost ◽  
Rapid Development ◽  
Battery Life ◽  
Portable Devices ◽  
Video Memory ◽  
Memory Design ◽  
On Chip ◽  
Viewing Context

With the rapid development of portable devices, it becomes more and more popular for people to watch videos by mobile phones. As people are enjoying to watch videos anytime and anywhere, experience and battery life are two major concerns. This paper presents a viewing context adaptive on-chip video memory design methodology to prolong the battery life of portable devices, while maintaining the viewing experience of users. We developed a model for mobile videos in different luminance contexts and based on it, implemented a low-cost low-power video memory. Our results show that up to 32.6% power savings can be achieved, while maintaining almost the same perception quality, as compared to the conventional SRAM.

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