Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.<br />The proposed memory cell is very stable during successive read operates and<br />comparatively faster and also occupies less amount of silicon area. The<br />stability of the data during successive read operation and noise margin are in<br />the promising range. Extensive simulation results using LTspice and<br />Cadence software tools demonstrate the validity and competency of the<br />proposed model.
Exploiting soft redundancy for error-resilient on-chip memory design