scholarly journals 6 Transistors and 1 Memristor based Memory Cell

2020 ◽  
Vol 9 (1) ◽  
pp. 42
Author(s):  
Kazi Fatima Sharif ◽  
Satyendra N. Biswas
Keyword(s):  
Memory Cell ◽  
Silicon Area ◽  
Memory Design ◽  
Hybrid Memory ◽  
Noise Margin ◽  
Proposed Model ◽  
New Type ◽  
On Chip ◽  
Stable Memory ◽  
Nmos Transistors

Area efficient and stable memory design is one of the most important tasks in designing system on chip. This research concentrates in designing a new type of hybrid memory model by using only nMOS transistors and memristor.<br />The proposed memory cell is very stable during successive read operates and<br />comparatively faster and also occupies less amount of silicon area. The<br />stability of the data during successive read operation and noise margin are in<br />the promising range. Extensive simulation results using LTspice and<br />Cadence software tools demonstrate the validity and competency of the<br />proposed model.

scholarly journals Design Issues for NEM-Relay-Based SRAM Devices

2018 ◽  
Vol 210 ◽  
pp. 01005
Author(s):  
Sebastià A. Bota ◽  
Jaume Verd ◽  
Xavier Gili ◽  
Joan Barceló ◽  
Gabriel Torrens ◽  
...  
Keyword(s):  
Strong Dependence ◽  
Memory Cell ◽  
Design Constraints ◽  
Cell Parameters ◽  
Hybrid Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Hybrid Devices ◽  
Static Noise ◽  
Selection Of

We analyze the design constraints of six transistor SRAM cells that arise when using nanoelectromechanical relays. Comparisons are performed between a CMOS 6T conventional SRAM cell and various hybrid memory cells built by replacing a selection of MOSFET transistors with NEM relays. Impact on important memory cell parameters such as various reliability metrics like static noise margin and write noise margin and power consumption are evaluated from circuit simulations using a Verilog-A compact model of the nanomechanical relay. We found that the use of relays involve a new challenge in the design of SRAM hybrid devices as the readability and writeability of the resulting cells manifests a strong dependence with the value of the contact resistance of the NEM relay, a parameter that can experience important variations with the continued operation of the device.

scholarly journals Impedance Modeling and Stability Analysis of DFIG-Based Wind Energy Conversion System Considering Frequency Coupling

Energies ◽  
2021 ◽  
Vol 14 (11) ◽  
pp. 3243
Author(s):  
Shaojian Song ◽  
Peichen Guan ◽  
Bin Liu ◽  
Yimin Lu ◽  
HuiHwang Goh
Keyword(s):  
Stability Analysis ◽  
Coupling Effect ◽  
Impedance Model ◽  
Wind Energy Conversion ◽  
Proposed Model ◽  
New Type ◽  
Impedance Modeling ◽  
Frequency Coupling ◽  
Bus Voltage ◽  
Voltage Dynamics

Impedance-based stability analysis is an effective method for addressing a new type of SSO accidents that have occurred in recent years, especially those caused by the control interaction between a DFIG and the power grid. However, the existing impedance modeling of DFIGs is mostly focused on a single converter, such as the GSC or RSC, and the influence between the RSC and GSC, as well as the frequency coupling effect inside the converter are usually overlooked, reducing the accuracy of DFIG stability analysis. Hence, the entire impedance is proposed in this paper for the DFIG-based WECS, taking coupling factors into account (e.g., DC bus voltage dynamics, asymmetric current regulation in the dq frame, and PLL). Numerical calculations and HIL simulations on RT-Lab were used to validate the proposed model. The results indicate that the entire impedance model with frequency coupling is more accurate, and it is capable of accurately predicting the system’s possible resonance points.

scholarly journals TRANSIENT RESPONSE OF A DISTRIBUTED RLC INTERCONNECT BASED ON DIRECT POLE EXTRACTION

2009 ◽  
Vol 18 (07) ◽  
pp. 1263-1285 ◽  
Author(s):  
GUOQING CHEN ◽  
EBY G. FRIEDMAN
Keyword(s):  
Closed Form ◽  
Transient Response ◽  
Transmission Lines ◽  
Average Error ◽  
Proposed Model ◽  
Newton Raphson ◽  
On Chip ◽  
Interconnect Systems ◽  
Interconnect System ◽  
Raphson Method

With higher operating frequencies, transmission lines are required to model global on-chip interconnects. In this paper, an accurate and efficient solution for the transient response at the far end of a transmission line based on a direct pole extraction of the system is proposed. Closed form expressions of the poles are developed for two special interconnect systems: an RC interconnect and an RLC interconnect with zero driver resistance. By performing a system conversion, the poles of an interconnect system with general circuit parameters are solved. The Newton–Raphson method is used to further improve the accuracy of the poles. Based on these poles, closed form expressions for the step and ramp response are determined. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. With two pairs of poles, the average error of the 50% delay is 1% as compared with Spectre simulations. With ten pairs of poles, the average error of the 10%-to-90% rise time and the overshoots is 2% and 1.9%, respectively. Frequency dependent effects are also successfully included in the proposed method and excellent match is observed between the proposed model and Spectre simulations.

scholarly journals Improvements on Learning Kernel Extended Dictionary for Face Recognition

2020 ◽  
Vol 34 (4) ◽  
pp. 387-394
Author(s):  
Soodabeh Amanzadeh ◽  
Yahya Forghani ◽  
Javad Mahdavi Chabok
Keyword(s):  
Sparse Representation ◽  
Face Image ◽  
Collaborative Representation ◽  
Training Images ◽  
Input Face ◽  
Proposed Model ◽  
Eigen Values ◽  
New Type ◽  
The Mean ◽  
Better Than

Kernel extended dictionary learning model (KED) is a new type of Sparse Representation for Classification (SRC), which represents the input face image as a linear combination of dictionary set and extended dictionary set to determine the input face image class label. Extended dictionary is created based on the differences between the occluded images and non-occluded training images. There are four defaults to make about KED: (1) Similar weights are assigned to the principle components of occlusion variations in KED model, while the principle components of the occlusion variations have different weights, which are proportional to the principle components Eigen-values. (2) Reconstruction of an occluded image is not possible by combining only non-occluded images and the principle components (or the directions) of occlusion variations, but it requires the mean of occlusion variations. (3) The importance and capability of main dictionary and extended dictionary in reconstructing the input face image is not the same, necessarily. (4) KED Runtime is high. To address these problems or challenges, a novel mathematical model is proposed in this paper. In the proposed model, different weights are assigned to the principle components of occlusion variations; different weights are assigned to the main dictionary and extended dictionary; an occluded image is reconstructed by non-occluded images and the principle components of occlusion variations, and also the mean of occlusion variations; and collaborative representation is used instead of sparse representation to enhance the runtime. Experimental results on CAS-PEAL subsets showed that the runtime and accuracy of the proposed model is about 1% better than that of KED.

scholarly journals An Efficient FPGA-Based Convolutional Neural Network for Classification: Ad-MobileNet

Electronics ◽  
2021 ◽  
Vol 10 (18) ◽  
pp. 2272
Author(s):  
Safa Bouguezzi ◽  
Hana Ben Fredj ◽  
Tarek Belabed ◽  
Carlos Valderrama ◽  
Hassene Faiedh ◽  
...  
Keyword(s):  
Recognition Rate ◽  
Hardware Acceleration ◽  
Implementation Model ◽  
Gate Arrays ◽  
Proposed Model ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Computer Vision Applications ◽  
On Chip ◽  
Segmentation Image

Convolutional Neural Networks (CNN) continue to dominate research in the area of hardware acceleration using Field Programmable Gate Arrays (FPGA), proving its effectiveness in a variety of computer vision applications such as object segmentation, image classification, face detection, and traffic signs recognition, among others. However, there are numerous constraints for deploying CNNs on FPGA, including limited on-chip memory, CNN size, and configuration parameters. This paper introduces Ad-MobileNet, an advanced CNN model inspired by the baseline MobileNet model. The proposed model uses an Ad-depth engine, which is an improved version of the depth-wise separable convolution unit. Moreover, we propose an FPGA-based implementation model that supports the Mish, TanhExp, and ReLU activation functions. The experimental results using the CIFAR-10 dataset show that our Ad-MobileNet has a classification accuracy of 88.76% while requiring little computational hardware resources. Compared to state-of-the-art methods, our proposed method has a fairly high recognition rate while using fewer computational hardware resources. Indeed, the proposed model helps to reduce hardware resources by more than 41% compared to that of the baseline model.

scholarly journals Enzyme catalysis as a chain reaction

1991 ◽  
Vol 279 (3) ◽  
pp. 855-861 ◽  
Author(s):  
S E Szedlacsek ◽  
R G Duggleby ◽  
M O Vlad
Keyword(s):  
Reaction Mechanism ◽  
Kinetic Mechanism ◽  
Point Of View ◽  
Simple Type ◽  
Chain Reaction ◽  
Proposed Model ◽  
New Type ◽  
A Chain ◽  
Theoretical Considerations ◽  
Classical Mechanism

A new type of enzyme kinetic mechanism is suggested by which catalysis may be viewed as a chain reaction. A simple type of one-substrate/one-product reaction mechanism has been analysed from this point of view, and the kinetics, in both the transient and the steady-state phases, has been reconsidered. This analysis, as well as literature data and theoretical considerations, shows that the proposed model is a generalization of the classical ones. As a consequence of the suggested mechanism, the expressions, and in some cases even the significance of classical constants (Km and Vmax.), are altered. Moreover, this mechanism suggests that, between two successive enzyme-binding steps, more than one catalytic act could be accomplished. The reaction catalysed by alcohol dehydrogenase was analysed, and it was shown that this chain-reaction mechanism has a real contribution to the catalytic process, which could become exclusive under particular conditions. Similarly, the mechanism of glycogen phosphorylase is considered, and two partly modified versions of the classical mechanism are proposed. They account for both the existing experimental facts and suggest the possibility of chain-reaction pathways for any polymerase.

Design of Low Power with Expanded Noise Margin Subthreshold 12T SRAM Cell for Ultra-Low Power Devices

2020 ◽  
pp. 2150106
Author(s):  
Harekrishna Kumar ◽  
V. K. Tomar
Keyword(s):  
Power Dissipation ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Time ◽  
Access Memory ◽  
Subthreshold Region ◽  
Noise Margin ◽  
Static Noise

In the proposed work, a differential write and single-ended read half-select free 12 transistors static random access memory cell is designed and simulated. The proposed cell has a considerable reduction in power dissipation with better stability and moderate performance. This cell operates in subthreshold region and has a higher value of read static noise margin as compared to conventional six transistors static random access memory cell. A power cut-off technique is utilized between access and pull-up transistors during the write operation. It results in an increase in write static noise margin as compared to all considered cells. In the proposed cell, read and write access time is improved along with a reduction in read/write power dissipation as compared to conventional six transistors static random access memory cell. The bitline leakage current in the proposed cell is reduced which improves the [Formula: see text] ratio of the cell under subthreshold region. The proposed cell occupies less area as compared to considered radiation-hardened design 12 transistors static random access memory cell. The computed electrical quality metric of proposed cell is better among considered static random access memory cells. Process variation analysis of read stability, access time, power dissipation, read current and leakage current has been performed with the help of Monte Carlo simulation at 3,000 points to get more soundness in the results. All characteristics of static random access memory cells are compared at various supply voltages.

scholarly journals Plasmonic nanogap enhanced phase-change devices with dual electrical-optical functionality

2019 ◽  
Vol 5 (11) ◽  
pp. eaaw2687 ◽  
Author(s):  
Nikolaos Farmakidis ◽  
Nathan Youngblood ◽  
Xuan Li ◽  
James Tan ◽  
Jacob L. Swett ◽  
...  
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Memory Cell ◽  
Communications Technologies ◽  
New Strategy ◽  
On Chip ◽  
Processing And Storage ◽  
Electrical Signaling ◽  
And Storage ◽  
Change Memory

Modern-day computers rely on electrical signaling for the processing and storage of data, which is bandwidth-limited and power hungry. This fact has long been realized in the communications field, where optical signaling is the norm. However, exploiting optical signaling in computing will require new on-chip devices that work seamlessly in both electrical and optical domains, without the need for repeated electrical-to-optical conversion. Phase-change devices can, in principle, provide such dual electrical-optical operation, but assimilating both functionalities into a single device has so far proved elusive owing to conflicting requirements of size-limited electrical switching and diffraction-limited optical response. Here, we combine plasmonics, photonics, and electronics to deliver an integrated phase-change memory cell that can be electrically or optically switched between binary or multilevel states. Crucially, this device can also be simultaneously read out both optically and electrically, offering a new strategy for merging computing and communications technologies.

scholarly journals Delay Bound Optimization in NoC Using a Discrete Firefly Algorithm

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1507
Author(s):  
Gaoming Du ◽  
Chao Tian ◽  
Zhenmin Li ◽  
Duoli Zhang ◽  
Chuan Zhang ◽  
...  
Keyword(s):  
Firefly Algorithm ◽  
Optimization Method ◽  
Video Object ◽  
Worst Case ◽  
Delay Bound ◽  
Proposed Model ◽  
Discrete Firefly Algorithm ◽  
Firefly Optimization ◽  
On Chip ◽  
Bound Optimization

The delay bound in system on chips (SoC) represents the worst-case traverse time of on-chip communication. In network on chip (NoC)-based SoC, optimizing the delay bound is challenging due to two aspects: (1) the delay bound is hard to obtain by traditional methods such as simulation; (2) the delay bound changes with the different application mappings. In this paper, we propose a delay bound optimization method using discrete firefly optimization algorithms (DBFA). First, we present a formal analytical delay bound model based on network calculus for both unipath and multipath routing in NoCs. We then set every flow in the application as the target flow and calculate the delay bound using the proposed model. Finally, we adopt firefly algorithm (FA) as the optimization method for minimizing the delay bound. We used industry patterns (video object plane decoder (VOPD), multiwindow display (MWD), etc.) to verify the effectiveness of delay bound optimization method. Experiments show that the proposed method is both effective and reliable, with a maximum optimization of 42.86%.

Design of a Stable Low Power 11-T Static Random Access Memory Cell

2020 ◽  
Vol 29 (13) ◽  
pp. 2050206 ◽  
Author(s):  
Ashish Sachdeva ◽  
V. K. Tomar
Keyword(s):  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Signal To Noise ◽  
Access Memory ◽  
Noise Margin ◽  
Sram Cell ◽  
Variation Tolerance ◽  
Read Signal

In this paper, a 11-T static random-access memory (SRAM) cell has been examined that shows a fair reduction in read power dissipation while upholding the stability and moderate performance. In the presented work, parametric variability analysis of various design metrices such as signal to noise margin, read current and read power of the Proposed 11T cell are presented and compared with few considered topologies. The Proposed cell offers single ended write operation and differential read operation. The improvement in read signal to noise margin and write signal to noise margin with respect to conventional 6T SRAM is 10.63% and 33.09%, respectively even when the write operation is single ended. Mean hold static noise margin of the cell for 3000 samples is [Formula: see text] times higher than considered D2p11T cell. Sensitivity analysis of data retention voltage (DRV) with respect to temperature variations is also investigated and compared with considered topologies. DRV variation with temperature is least in FF process corner. In comparison to conventional 6T SRAM cell, the write and read delay of Proposed 11T cell gets improved by [Formula: see text] and 1.64%, respectively. Proposed 11T topology consumes least read energy in comparison with considered topologies. In comparison with another considered 11T topology, i.e., D2p11T cell, Proposed cell consumes 13.11% lesser area. Process variation tolerance with Monte Carlo simulation for read current and read power has been investigated using Cadence virtuoso tool with GPDK 45-nm technology.

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