Comprehensive study of error detection by cyclic redundancy check

2017 ◽  
Author(s):  
Anil Kumar Singh
Keyword(s):  
Error Detection ◽  
Cyclic Redundancy Check ◽  
Comprehensive Study

scholarly journals Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

2020 ◽  
Author(s):  
Huan Liu ◽  
Zhiliang Qiu ◽  
Weitao Pan ◽  
Jun Li ◽  
Ling Zheng ◽  
...  
Keyword(s):  
Resource Utilization ◽  
Error Detection ◽  
High Performance ◽  
State Of The Art ◽  
Low Cost ◽  
Source Code ◽  
Experimental Results ◽  
Extended Version ◽  
Cyclic Redundancy Check

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

scholarly journals CRC 8-bit Encoder-Decoder Component in FPGA using VHDL

2020 ◽  
Vol 8 (1) ◽  
pp. 58
Author(s):  
ANDHI RACHMAN SALEH ◽  
SUNNY ARIEF SUDIRO
Keyword(s):  
Error Detection ◽  
Data Transmission ◽  
Cyclic Codes ◽  
High Reliability ◽  
Asynchronous Transfer Mode ◽  
Integrated Services ◽  
Integrated Services Digital Network ◽  
Cyclic Redundancy Check ◽  
Transfer Mode ◽  
Digital Network

AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli. CRC memiliki keandalan yang tinggi dalam pengiriman data karena CRC menggunakan algoritma berdasarkan cyclic code. Pada artikel ini generator polinomial yang digunakan dalam encoder dan decoder adalah CCITT  dan dengan lebar bit data 8 bit. CRC-8-CCITT biasanya digunakan pada Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, dll. Pada penelitian ini dilakukan perancangan dan diterapkan dengan menggunakan VHDL. Software pendukung yang digunakan untuk mengimplementasikan VHDL adalah Xilinx ISE 8.1i.Kata kunci: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1iAbstractCyclic Redundancy Check (CRC) is one type of error detection used in data transmission. CRC commonly used in digital networks and storage devices to detect accidental changes to raw data. CRC has high reliability in data transmission because uses algorithms based on cyclic codes. In this article the polynomial generator used in the encoder and decoder is the CCITT  and with a width of 8 bits data bits.CRC-8-CCITT usually used at Asynchronous Transfer Mode (ATM) headers, Integrated Services Digital Network (ISDN) HEC, etc. This article presents design and implementation of a component using VHDL. The supporting software used to implement VHDL is Xilinx ISE 8.1i.Keywords: Cyclic Redundancy Check (CRC), VHDL Language, Xilinx ISE 8.1i

scholarly journals Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

2020 ◽  
Author(s):  
Huan Liu ◽  
Zhiliang Qiu ◽  
Weitao Pan ◽  
Jun Li ◽  
Ling Zheng ◽  
...  
Keyword(s):  
Resource Utilization ◽  
Error Detection ◽  
High Performance ◽  
State Of The Art ◽  
Low Cost ◽  
Source Code ◽  
Experimental Results ◽  
Extended Version ◽  
Cyclic Redundancy Check

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 84.1% and 37.6% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 83.9% and 8.9% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

scholarly journals Low-Cost and Programmable CRC Implementation based on FPGA

2020 ◽  
Author(s):  
Huan Liu ◽  
Zhiliang Qiu ◽  
Weitao Pan ◽  
Jun Li ◽  
Ling Zheng ◽  
...  
Keyword(s):  
Resource Utilization ◽  
Error Detection ◽  
High Performance ◽  
State Of The Art ◽  
Low Cost ◽  
Source Code ◽  
Experimental Results ◽  
Cyclic Redundancy Check

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 84.1% and 37.6% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 83.9% and 8.9% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

scholarly journals Low-Cost and Programmable CRC Implementation based on FPGA (Extended Version)

2020 ◽  
Author(s):  
Huan Liu ◽  
Zhiliang Qiu ◽  
Weitao Pan ◽  
Jun Li ◽  
Ling Zheng ◽  
...  
Keyword(s):  
Resource Utilization ◽  
Error Detection ◽  
High Performance ◽  
State Of The Art ◽  
Low Cost ◽  
Source Code ◽  
Experimental Results ◽  
Extended Version ◽  
Cyclic Redundancy Check

Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability further exacerbate this problem. In this brief, the stride-by-5 algorithm is proposed to achieve the optimal utilization of FPGA resources. The pipelining go back algorithm is proposed to solve the padding zeros problem. The method of reprogramming by HWICAP is proposed to realize programmability with a small and constant resource utilization. The experimental results show that the resource utilization of proposed non-segmented architecture is 80.7%-87.5% and 25.1%-46.2% lower than those of two state-of-the-art FPGA-based CRC implementations, and the proposed segmented architecture has a lower resource utilization by 81.7%-85.9% and 2.9%-20.8% compared wtih the two state-of-the-art architectures; meanwhile, the throughput and programmability are guaranteed. We made the source code available on GitHub.

scholarly journals Area efficient parallel lfsr for cyclic redundancy check

2020 ◽  
Vol 10 (2) ◽  
pp. 1755
Author(s):  
Rita Mahajan ◽  
Komal Devi ◽  
Deepak Bagai
Keyword(s):  
Data Storage ◽  
Error Detection ◽  
Parallel Implementation ◽  
Search Algorithm ◽  
Clock Cycle ◽  
Linear Feedback ◽  
Cyclic Redundancy Check ◽  
Polynomial Degree ◽  
Data Message ◽  
State Space Transformation

Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.

Progress In The Practical Application Of Automated Image Analysis To Tem Negatives

1977 ◽  
Vol 35 ◽  
pp. 214-217
Author(s):  
F. A. Heckman ◽  
E. Redman ◽  
J.E. Connolly
Keyword(s):  
Image Analysis ◽  
Image Quality ◽  
Exposure Time ◽  
Image Contrast ◽  
Automated Image Analysis ◽  
Practical Application ◽  
Factors Affecting ◽  
High Image Quality ◽  
Qualitative Evidence ◽  
Comprehensive Study

In our initial publication on this subject1) we reported results demonstrating that contrast is the most important factor in producing the high image quality required for reliable image analysis. We also listed the factors which enhance contrast in order of the experimentally determined magnitude of their effect. The two most powerful factors affecting image contrast attainable with sheet film are beam intensity and KV. At that time we had only qualitative evidence for the ranking of enhancing factors. Later we carried out the densitometric measurements which led to the results outlined below.Meaningful evaluations of the cause-effect relationships among the considerable number of variables in preparing EM negatives depend on doing things in a systematic way, varying only one parameter at a time. Unless otherwise noted, we adhered to the following procedure evolved during our comprehensive study:Philips EM-300; 30μ objective aperature; magnification 7000- 12000X, exposure time 1 second, anti-contamination device operating.

Hexachlorobenzene toxicity in the monkey ovary: III. Ultrastructure induced by high (10 mg/kg) dose exposure

1991 ◽  
Vol 49 ◽  
pp. 130-131
Author(s):  
A. Singh ◽  
A. Dykeman ◽  
J. Jarrelf ◽  
D. C. Villeneuve
Keyword(s):  
Present Report ◽  
Reproductive Toxicity ◽  
Control Group ◽  
Primate Model ◽  
Human Follicular Fluid ◽  
Thin Sections ◽  
Cynomolgus Monkeys ◽  
Cacodylate Buffer ◽  
Induction Cycle ◽  
Comprehensive Study

Hexachlorobenzene (HCB), a persistent and mobile organochlorine pesticide, occurs in environment. HCB has been shown to be present in human follicular fluid. An objective of the present report, which is part of a comprehensive study on reproductive toxicity of HCB, was to determine the cytologic effects of the compound on ovarian follicles in a primate model.Materials and Methods. Eight Cynomolgus monkeys were housed under controlled conditions at Animal facility of Health and Welfare, Ottawa. Animals were orally administered gelatin capsules containing HCB mixed with glucose in daily dosages of 0.0 or 10 mg/kg b.w. for 90 days; the former was the control group. On the menstrual period following completion of dosing, the monkeys underwent an induction cycle of superovulation. At necropsy, one-half of an ovary from each animal was diced into ca. 2- to 3-mm cubed specimens that were fixed by immersion in 2.5% glutaraldehyde in 0.1 M cacodylate buffer (pH 7.3). Subsequent procedures followed to obtain thin sections that were examined in a Hitachi H-7000 electron microscope have been described earlier.

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