Impact of Asymmetric Channel Configuration on the Linearity of Double-Gate SOI MOSFETs

2006 ◽  
Author(s):  
Marcelo Pavanello ◽  
Antonio Cerdeira ◽  
Joao Martino ◽  
Jean-pierre Raskin ◽  
Denis Flandre
Keyword(s):  
Double Gate ◽  
Asymmetric Channel ◽  
Channel Configuration

Modeling Aspects of Asymmetric Channel Configuration DPFs

2009 ◽  
Author(s):  
Weiyong Tang ◽  
Syed Wahiduzzaman ◽  
Seth Wenzel ◽  
Wen Wang
Keyword(s):  
Asymmetric Channel ◽  
Channel Configuration

scholarly journals Optimal inverter logic gate using 10-nm double gate-all-around (DGAA) transistor with asymmetric channel width

AIP Advances ◽  
2016 ◽  
Vol 6 (1) ◽  
pp. 015311
Author(s):  
Myunghwan Ryu ◽  
Franklin Bien ◽  
Youngmin Kim
Keyword(s):  
Logic Gate ◽  
Channel Width ◽  
Double Gate ◽  
Asymmetric Channel

Laterally asymmetric channel engineering in fully depleted double gate SOI MOSFETs for high performance analog applications

2004 ◽  
Vol 48 (6) ◽  
pp. 947-959 ◽  
Author(s):  
Abhinav Kranti ◽  
Tsung Ming Chung ◽  
Denis Flandre ◽  
Jean-Pierre Raskin
Keyword(s):  
High Performance ◽  
Double Gate ◽  
Asymmetric Channel ◽  
Fully Depleted ◽  
Channel Engineering

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

2009 ◽  
Vol E92-C (5) ◽  
pp. 659-663 ◽  
Author(s):  
Doo-Hyun KIM ◽  
Il Han PARK ◽  
Seongjae CHO ◽  
Jong Duk LEE ◽  
Hyungcheol SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Double Gate ◽  
Gate Structure ◽  
Retention Characteristics

Independent-Double-Gate FinFET SRAM Technology

2013 ◽  
Vol E96.C (4) ◽  
pp. 413-423 ◽  
Author(s):  
Kazuhiko ENDO ◽  
Shin-ichi OUCHI ◽  
Takashi MATSUKAWA ◽  
Yongxun LIU ◽  
Meishoku MASAHARA
Keyword(s):  
Double Gate
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