Independent-Double-Gate FinFET SRAM Technology

2013 ◽  
Vol E96.C (4) ◽  
pp. 413-423 ◽  
Author(s):  
Kazuhiko ENDO ◽  
Shin-ichi OUCHI ◽  
Takashi MATSUKAWA ◽  
Yongxun LIU ◽  
Meishoku MASAHARA
Keyword(s):  
Double Gate

Simulation of Retention Characteristics in Double-Gate Structure Multi-Bit SONOS Flash Memory

2009 ◽  
Vol E92-C (5) ◽  
pp. 659-663 ◽  
Author(s):  
Doo-Hyun KIM ◽  
Il Han PARK ◽  
Seongjae CHO ◽  
Jong Duk LEE ◽  
Hyungcheol SHIN ◽  
...  
Keyword(s):  
Flash Memory ◽  
Double Gate ◽  
Gate Structure ◽  
Retention Characteristics

Circuit Design of Reconfigurable Logic Based on Double-Gate CNTFETs

2013 ◽  
Vol E96.A (7) ◽  
pp. 1642-1644
Author(s):  
Manabu KOBAYASHI ◽  
Hiroshi NINOMIYA ◽  
Shigeyoshi WATANABE
Keyword(s):  
Circuit Design ◽  
Double Gate ◽  
Reconfigurable Logic

Analysis of dependence of dV CE/dt on turn-off characteristics with a 1200 V double-gate insulated gate bipolar transistor

2021 ◽  
Vol 60 (SB) ◽  
pp. SBBD02
Author(s):  
Yoko Iwakaji ◽  
Tomoko Matsudai ◽  
Tatsunori Sakano ◽  
Kazuto Takao
Keyword(s):  
Bipolar Transistor ◽  
Double Gate ◽  
Insulated Gate Bipolar Transistor

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Double-Gate W-Doped Amorphous Indium Oxide Transistors for Monolithic 3D Capacitorless Gain Cell eDRAM

2020 ◽  
Author(s):  
H. Ye ◽  
J. Gomez ◽  
W. Chakraborty ◽  
S. Spetalnick ◽  
S. Dutta ◽  
...  
Keyword(s):  
Indium Oxide ◽  
Double Gate

Double‐Gate MoS 2 Field‐Effect Transistors with Full‐Range Tunable Threshold Voltage for Multifunctional Logic Circuits

2021 ◽  
pp. 2101036
Author(s):  
Jiali Yi ◽  
Xingxia Sun ◽  
Chenguang Zhu ◽  
Shengman Li ◽  
Yong Liu ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Full Range ◽  
Logic Circuits ◽  
Double Gate

Effect of Underlap with Fixed Gate Length: GaN-Based Double-Gate MOSFETs

2021 ◽  
Author(s):  
Md. Rokib Hasan ◽  
Md. Rabiul Islam ◽  
Tanjim Masroor Bhuiyan ◽  
Muhib Ashraf Nibir ◽  
Md. Emran Hasan ◽  
...  
Keyword(s):  
Gate Length ◽  
Double Gate
Sign in / Sign up

Export Citation Format

Share Document